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Title:
SELF CLOCK LOGIC CIRCUIT AND METHOD FOR LATCHING ITS OUTPUT SIGNAL
Document Type and Number:
Japanese Patent JPH11185492
Kind Code:
A
Abstract:

To improve speed of a sequential logic circuit by using a delay line technique and making the logic circuit clock with a self timing in response to an input signal.

A register 100 is to latched in response to an input effective signal VI composed of N bits, and inputs I1-IN are input a first logic block 102, where a function F is calculated and M bit outputs F1-FM are generated. The bit outputs are input to a second logic block 106 through a register 104, a function G is calculated on the basis of the bits F1-FM and L bit outputs G1-GL, are generated. The bit outputs are output from a register 108. In the meantime, effective signals VI', VF, VF', VG are generated correspondingly to delay amounts of the register 100, logic circuit 102, register 104 and logic circuit 106 by delay lines 110, 112, 114, 116. The VG, VF signals are bit latched as clock signals of the registers 104, 106 respectively. Each register can latch outputs immediately in synchronization with the corresponding logic circuit.


Inventors:
RICHARD RELPH
Application Number:
JP1998000174641
Publication Date:
July 09, 1999
Filing Date:
June 22, 1998
Export Citation:
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Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
G11C19/00; H03K3/02; H03K3/037; H03K19/00; (IPC1-7): G11C19/00; H03K3/02
Attorney, Agent or Firm:
深見 久郎 (外3名)