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Title:
SEMICONDUCTOR CHIP LAMINATE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2008084972
Kind Code:
A
Abstract:

To provide a semiconductor chip laminate in which a part of an end of an upper layer semiconductor chip protrudes toward a side beyond an end of a lower layer semiconductor chip, connection failure is prevented in an electric connection terminal positioned on a lower part of a protruding portion and deformation of the upper layer semiconductor chip is suppressed.

The semiconductor chip laminate 1 is provided with a substrate or a first semiconductor chip 2 and second and third semiconductor chips 3, 4. At least a part of an end 4a of the third semiconductor chip 4 protrudes toward the side beyond the end 3a of the second semiconductor chip 3. Between an electric connection terminal 2a and the end 3a of the second semiconductor chip 3, a supporting layer 9 is provided so as not to reach the first electric connection terminal 2a between the bottom surface of a protruding portion 4A and the top surface of the substrate or the top surface of the semiconductor chip 2.


Inventors:
ISHIZAWA HIDEAKI
HAYAKAWA AKINOBU
Application Number:
JP2006261179A
Publication Date:
April 10, 2008
Filing Date:
September 26, 2006
Export Citation:
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Assignee:
SEKISUI CHEMICAL CO LTD
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
JP2005340415A2005-12-08
JP2005302815A2005-10-27
Attorney, Agent or Firm:
Miyazaki saki main tax
Makoto