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Patent Searching and Data


Title:
SEMICONDUCTOR CHIP WITH BUMP
Document Type and Number:
Japanese Patent JPH1187418
Kind Code:
A
Abstract:

To suppress the generation of a void by a method wherein electrodes are arranged along each side of a surface of the chip body, and the bumps, having the oval-shaped junction surface of each electrode, are formed on the electrodes.

Electrodes 13 are formed along each side of one surface of a chip body 12, and bumps 31 are formed on the electrodes 13. The junction surface of each bump 31 with the electrodes 13 is oval shaped, and the longitudinal direction of the oval shaped bump 31 is formed in the direction orthogonally intersecting with the side along the bumps 31. Consequently, a wide chip 32 can be obtained between the adjacent bumps 31, and sealing resin easily passes between the bumps 31 when they are mounted on a substrate. To be more precise, the sealing resin is allowed to flow uniformly and the entainment of air is suppressed, and as a result, the generation of voids in the sealing resin can be suppressed.


Inventors:
YAMAGUCHI TATSUYA
SAITO YOSHIO
Application Number:
JP1997000239666
Publication Date:
July 26, 1989
Filing Date:
September 04, 1997
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/304; G01F23/28; G01F23/292; G03F1/84; (IPC1-7): G01F23/28; H01L21/304
Attorney, Agent or Firm:
草野 卓 (外1名)