SEMICONDUCTOR DEVICE AND FABRICATION THEREOF

Japanese Patent JP3520697

B2

PROBLEM TO BE SOLVED: To prevent short-circuiting lot upper and lower interconnections at the time of forming a contact hole selfaligned with the interconnection by a structure wherein the end face of a first silicon dioxide deposited on a conductive layer is present on the inside of a first silicon nitride to be deposited.
SOLUTION: At the time of depositing a silicon dioxide 8 and a silicon nitride 2 on a conductive layer 1 formed on a substrate and patterning an interconnection, the first silicon nitride 2 is etched using a resist layer 9 as a mask and then the silicon dioxide 8 is etched isotropically. Subsequently, the conductive layer 1 is subjected to anisotropic etching and a thermal oxide 6 is deposited on the side face of the conductive layer 1. Thereafter, a second silicon nitride is deposited on the substrate and etched back to form a side wall 4. Finally, an interlayer insulator 5 is deposited and a contact hole is made while being self-aligned with the interconnection. According to the method, short circuit of upper and lower interconnections can be prevented at the time of forming a contact hole self-aligned with the interconnection.

Okawa, Shigemi

JP29502196A

April 19, 2004

November 07, 1996

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FUJITSU LTD

H01L21/283; H01L21/28; H01L21/768; H01L23/522; H01L29/78; (IPC1-7): H01L21/768; H01L21/28; H01L21/283; H01L29/78

横山 淳一

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