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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS615566
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of a parasitic MOSFET in a microstructure bipolar-type semiconductor IC circuit device by a method wherein conductive impurity concentration in the vicinity of a linear element is selectively enriched.

CONSTITUTION: On a semiconductor base body, an npn type bipolar transistor Q1 that is a linear element and an IIL that is a digital element are formed in coexistence. The base body is an n- type epitaxial layer 14 formed on a p- type silicon semiconductor substrate 10. In a region a1, an n type diffusion layer 22 is selectively formed in the field of the bipolar transistor Q1 except in the region occupied by a p type base diffusion layer 26 for the selective enrichment of conductive impurity concentration in the epitaxial layer 14. This design eliminates the possibilities for a channel inversion layer to be created to serve as a leak current path in the surface of the region a1, which substantially elevates the threshold value against a parasitic MOSFET that may appear in the vicinity of the linear element.


Inventors:
HAIJIMA MIKIO
Application Number:
JP12517084A
Publication Date:
January 11, 1986
Filing Date:
June 20, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/8226; H01L27/02; H01L27/082; (IPC1-7): H01L27/06; H01L27/08
Attorney, Agent or Firm:
Akio Takahashi



 
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