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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2014056864
Kind Code:
A
Abstract:

To enable formation of a pillar and a hole pattern by an LELE (Litho-Etching-Litho-Etching) method by an L/S (Line and Space) pattern using SPT (Spacer Patterning Transfer) and adjust a pattern without necessitating an additional process.

A semiconductor device manufacturing method comprises: forming on a substrate, a first core material pattern 11 having a non-periodic part in a part of L/S; forming first sidewall films 12 on sidewalls of the core material pattern 11 after thinning the core material pattern 11; subsequently forming a first layer mask pattern 13 composed of the sidewall films 12 by removing the core material pattern 11; subsequently forming a second core material pattern 21 having the L/S on the first layer mask pattern 13; forming second sidewall films 22 on sidewalls of the core material pattern 21 after thinning the core material pattern 21; subsequently forming a second layer mask pattern 23 composed of the sidewall films 22 by removing the core material pattern 21; and subsequently, selectively processing the substrate by using the first layer and the second layer mask patterns 13, 23.


Inventors:
NAKAZAWA TAKASHI
Application Number:
JP2012000199399
Publication Date:
March 27, 2014
Filing Date:
September 11, 2012
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/027; H01L21/3065; H01L21/3205; H01L21/768
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Nakamura Makoto
Nobuhisa Nogawa
Ryuji Mine
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi