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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3836189
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To enhance the digital frequency(DF) regulation rate while reducing the area of IC by storing a data in a first dielectric breakdown type P-ROS element and determining the breakdown strength of the first P-MOS element using a second dielectric breakdown type P-ROS element.
SOLUTION: An IC is operated at first and when a set pseudo data is not delivered from the 256Hz I/O terminal 106 for testing, it means breakdown of a P-ROM 216 for DF data or trouble of a DF regulation circuit. When a set pseudo data is delivered, writing is performed without specifying an address for the DF data at a voltage lower than the standard writing voltage of the P-ROM 216 before the IC is operated. When a set pseudo data is not delivered from the output of the output terminal 106, it means an unacceptable low breakdown strength of the P-ROM 216. When a set pseudo data is delivered after writing at the standard writing voltage, it means an unacceptable high breakdown strength of the P-ROM 216. When a set pseudo data is not delivered, it means an acceptable breakdown strength.


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Inventors:
戸川 隆史
Application Number:
JP19196996A
Publication Date:
October 18, 2006
Filing Date:
July 22, 1996
Export Citation:
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Assignee:
シチズン時計株式会社
International Classes:
G04G3/00; G04G3/02; H03B5/32; (IPC1-7): G04G3/00; G04G3/02; H03B5/32
Domestic Patent References:
JP57191900A
JP58161199A
JP60131700A
JP61024667B1