Title:
SEMICONDUCTOR INPUT CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3373795
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a semiconductor input circuit where a through-current is eliminated, while properly reflecting a logic level of an external input signal onto the inside of the circuit in a test mode.
SOLUTION: This semiconductor input circuit is provided with a differential amplifier circuit which has a current mirror circuit consisting of 1st conduction type 1st and 2nd MOS transistors(TRs) 11, 12, whose gates respectively receive an external input signal and a reference level signal and whose sources are connected in common and of 2nduction type two MOS TRs 21, 22 whose drains are connected respectively to drains of the 1st and 2nd MOS TRs 11, 12. In this case, a transfer gate 30 that is on/off-controlled by a test use control signal is connected between the gate node of the current mirror circuit and an external input node, to which the external input signal is applied.
Inventors:
Nobuaki Ohtsuka
Osamu Hirabayashi
Osamu Hirabayashi
Application Number:
JP27218698A
Publication Date:
February 04, 2003
Filing Date:
September 25, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/28; G11C11/401; G11C11/409; H01L21/8238; G11C29/00; G11C29/12; H01L27/092; H03K19/00; H03K19/0175; (IPC1-7): H03K19/0175; H03K19/00
Domestic Patent References:
| JP4258020A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)
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