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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH01231350
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of junction leakage due to the counter diffusion of impurities and a defective contact by forming a high melting-point metallic silicide wiring using a titanium silicide and setting impurity concentration in an N-type impurity diffusion layer at a value lower than impurity concentration in a P-type impurity diffusion layer.

CONSTITUTION: Source-drain regions 29, 30 in a P channel transistor and an N channel transistor are connected by the wiring 36 of titanium silicide, and impurity concentration in the source-drain region 30 in the N channel transistor is set at a value lower than impurity concentration in the source drain region 29 in the P channel transistor. According to such a device, the diffusion of a P-type impurity through the wiring is prevented. Consequently, even when an N-type impurity such as As, P, etc., in the source-drain region 30 in the N channel transistor is diffused into the P+ source-drain region 29 in the P channel transistor through the titanium silicide wiring 36, the P type of the region 29 is not inverted into an N type, and junction leakage and a defective contact are not caused.


Inventors:
IDA JIRO
SAWACHI MASAO
Application Number:
JP5626988A
Publication Date:
September 14, 1989
Filing Date:
March 11, 1988
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L21/3205; H01L21/28; H01L21/8238; H01L23/52; H01L27/08; H01L27/092; (IPC1-7): H01L21/88; H01L27/08
Attorney, Agent or Firm:
Hiroshi Kikuchi