Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4032066
Kind Code:
B2
Abstract:
A semiconductor integrated circuit includes a voltage generating circuit configured to generate a predetermined voltage, an NMOS transistor configured to receive at a gate node thereof the predetermined voltage generated by the voltage generating circuit, to receive at a drain node thereof an external power supply voltage, and to generate at a source node thereof a stepped-down voltage by reducing the external power supply voltage in response to the predetermined voltage, and a PMOS transistor, provided between the drain node of the NMOS transistor and the external power supply voltage, configured to receive at a gate node thereof a power-down signal indicative of a power-down mode. The predetermined voltage applied to the gate node of the NMOS transistor is set to LOW in response to a HIGH state of the power-down signal applied to the gate node of the PMOS transistor.
Inventors:
Atsushi Takeuchi
Application Number:
JP2005503227A
Publication Date:
January 16, 2008
Filing Date:
June 27, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K19/096; G05F3/24; H01L21/822; H01L27/04; H02M3/07; H03K4/02; H03K19/00
Domestic Patent References:
| JP2002124084A | ||||
| JP11066855A | ||||
| JP2001068626A | ||||
| JP5054649A | ||||
| JP6326194A | ||||
| JP6208789A | ||||
| JP2004129019A |
Attorney, Agent or Firm:
Tadahiko Ito