PURPOSE: To obtain a decode circuit in which the delayed time of delay circuit is made variable in order to maintain a stable operation at the time of a write-in while using a self-resetting circuit suitable to high-speed operation as a decode circuit.
CONSTITUTION: In the self-resetting circuit, inputs of a delay circuit 950 generating reset signals 31, 32 being in phase with an output signal 20 being delayed by a prescribed time are made the output signal 20 and a pulse width control signal 40 and the pulse width of the output signal 20 is varied by changing times when the pulse width control signal 40 becomes a high level. Further, a latch circuit 201 holding the potential of the output signal 20 is added in this circuit. As a result, the pulse width of the output signal 20 can be made wider than pulse widths of input signals 10, 11 and the output potential 20 is prevented from being lowered with elements 400, 401, and 200 imparting direct-currently a potential to the output by adding the latch circuit 201 holding the potential of the output signal 20.
HIGUCHI HISAYUKI
NAKAGOME YOSHINOBU
SASAKI KATSURO
