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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH1145224
Kind Code:
A
Abstract:

To provide an LSI with built-in storage element which enables address space expansion of almost power multiplication without increasing the number of terminals.

A register array 13 where address specification and data transfer are performed on a time-division basis through a bus terminal is incorporated and the address space of the register array 13 is expanded without increasing the number of terminals. The register array 13 is divided into banks and has an address specifying circuit 14 which inputs and holds an address so as to access them. A specific address FFh in a bank is inhibited from being used under normal conditions and the address specifying circuit 14 holds a bank address specifying one bank in the register array 13 in a bank register 24 when the specific address FFh is inputted and the bank address is inputted in successive data read/write mode. The register array can be accessed with this bank address and the low-order address held in the address register 22.


Inventors:
OKADA KENICHI
Application Number:
JP20318997A
Publication Date:
February 16, 1999
Filing Date:
July 29, 1997
Export Citation:
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Assignee:
YAMAHA CORP
International Classes:
G06F13/16; G10H7/02; (IPC1-7): G06F13/16; G10H7/02
Attorney, Agent or Firm:
Itami Masaru



 
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