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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS63256011
Kind Code:
A
Abstract:

PURPOSE: To prevent the operating speed of semiconductor integrated circuit due to charging/discharge time by setting a charging potential of a connecting point desired to be charged in a semiconductor integrated circuit depending on a logic threshold voltage of a logic gate.

CONSTITUTION: Supposing that a connecting point 415 is a ground potential, then an output of a NOR gate 404 is at H and a transistor (TR) 403 is conductive. The potential of a connecting point 415 is increased through the charging by a MIS P-channel TR 401 and a MIS N-channel TR 403 from a high potential power supply 412. When the potential exceeds the logic gate threshold value of a NOR gate 404, the output of a NOR gate 404 goes to L and the TR 403 is nonconductive. The connecting point 415 is charged up to the logical threshold value of the NOR gate 404 and its charging potential does not reach the potential of a high potential power supply 412. Moreover, the charging time is short and the charging current is enough to be small because the potential to be charged to the connecting point 415 is lower than the potential of the high voltage power supply.


Inventors:
KONDOU IRIYOSHI
Application Number:
JP1987000091155
Publication Date:
October 24, 1988
Filing Date:
April 13, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/088; G11C11/34; H01L21/8234; H01L27/08; H03K4/94; H03K5/02; H03K5/08; H03K19/096; (IPC1-7): G11C11/34; H01L27/08; H03K4/94; H03K5/08; H03K19/096



 
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