Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2008176910
Kind Code:
A
Abstract:
To make erroneous reading of a semiconductor memory device less likely to occur or realize reduction of power consumption in a simple manner.
In an N-well region 151 on a semiconductor substrate, P-channel transistors 106 and 107 are formed. In P-well regions 152 and 153 arranged in both sides of the N-well region 151, N-channel transistors 108 and 109 and the like are formed. Respective gate lengths (widths of gate electrodes) A, B and C of the N-channel transistor 108, read drive transistor 120 and read access transistor 122 are set so that AB, AC and CB.
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Inventors:
ISHIKURA SATOSHI
KURUMADA MAREFUSA
OKUYAMA HIROAKI
YAMAGAMI YOSHINOBU
TERANO TOSHIO
KURUMADA MAREFUSA
OKUYAMA HIROAKI
YAMAGAMI YOSHINOBU
TERANO TOSHIO
Application Number:
JP2007327066A
Publication Date:
July 31, 2008
Filing Date:
December 19, 2007
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11C11/41; H01L21/8244; H01L27/11
Domestic Patent References:
| JP2003223788A | 2003-08-08 | |||
| JP2005228468A | 2005-08-25 |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
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