Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4162076
Kind Code:
B2
Abstract:
An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.
Inventors:
Masanao Yamaoka
Kenichi Nagata
Kenichi Nagata
Application Number:
JP2002156646A
Publication Date:
October 08, 2008
Filing Date:
May 30, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/413; G11C11/417; G11C11/419; G11C11/4193; G11C29/02
Domestic Patent References:
| JP62289994A | ||||
| JP2000268574A |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka
Yasuo Sakuta
Yasuo Sakuta