Title:
SEMICONDUCTOR MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH1083677
Kind Code:
A
Abstract:
To contrive rationalization of activating timing margin of a sense amplifier.
This device is provided with a detecting means 10 detecting dispersion of process of a delay time in a delay stage, and a delay time correcting means 11 correcting a delay time of a clock in the delay stage based on a detected result of the detecting means 10, and rationalization of activating timing margin of the sense amplifier is achieved by correcting a delay time of a clock in the delay stage based on the detected result of the detecting means 10.
Inventors:
SUZUKI TAKESHI
FUJIMURA YASUHIRO
ANDO KAZUMASA
FUJIMURA YASUHIRO
ANDO KAZUMASA
Application Number:
JP23779596A
Publication Date:
March 31, 1998
Filing Date:
September 09, 1996
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/413; G11C11/407; G11C11/409; G11C11/419; (IPC1-7): G11C11/419; G11C11/413
Attorney, Agent or Firm:
Tamamura Shizuyo