To provide a semiconductor memory which can shorten a time required for processing data at the memory test and normal operation.

A latch circuit 11 holds reading out data of a memory cell 5, and outputs it to an external device and a data inversion circuit 13. The data inversion circuit 13 inverts data with the same cycle as a read-out cycle, and gives it to an input terminal B of a selector 9. The selector 9 selects inversion data by an instruction signal S, and outputs it to a write-in circuit 7. The write-in circuit 7 writes inversion data in the memory 5.