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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH03256296
Kind Code:
A
Abstract:

PURPOSE: To stabilize operation extending over a wide range by impressing always supply potential to the gate electrode of an N-channel type transistor (TR) inserted in series between the source electrode of a P-channel type TR and power supply.

CONSTITUTION: The N-channel type TR 8 is inserted between the power supply VDD and the source electrode of the P-channel type TR 9 to constitute a CMOS inverting amplifier 11 for data sense. Here, the supply potential VCC is impressed to the gate electrode of the TR 8, and the source potential of the TR 9 is lowered. Then, the ratio of the channel widths of the TR 9 and the N-channel type TR 10 can be set nearly the same as a usual inverting amplifier. Then, the stable operation can be realized extending over a wide supply voltage range and a wide wafer process parameter range.


Inventors:
MATSUMOTO NORIMASA
SHINOHARA HIROSHI
Application Number:
JP5686490A
Publication Date:
November 14, 1991
Filing Date:
March 07, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C11/419; (IPC1-7): G11C11/419