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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS6177199
Kind Code:
A
Abstract:

PURPOSE: To obtain a circuit construction capable of performing a page mode write peculiar to an EEPROM efficiently by providing a switching transistor between a data detecting memory means and a bit line and controlling it according to respective operation condition.

CONSTITUTION: In case of reading a data, transistors Tr32, 34 are turned on, and in case when the memory cell 15 of a bit line 11 is selected correspondingly to an address, the dummy cell 18 of other bit line 12 is selected. When lowerings of the electric potential of the lines 11, 12 are different and the difference of the electric potential becomes fully large, Tr28, 29 in a data detecting memory circuit 20 are turned on, an FF31 is operable and a reading data is stored in an FF27. The data is outputted through an output buffer 45. In case of a data writing, the Tr32, 34 are turned off, the FF31 is operable, the data is fed through an input buffer 46 to an input data setting circuit 47, and stored in the FF27. The respective input data setting circuit 47 carries out a data storage in a page mode write.


Inventors:
MIYAMOTO JUNICHI
TSUJIMOTO JUNICHI
Application Number:
JP1984000197925
Publication Date:
April 19, 1986
Filing Date:
September 21, 1984
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C17/00; G11C16/02; G11C16/06; G11C16/28; (IPC1-7): G11C17/00