Title:
SEMICONDUCTOR MODULE AND MANUFACTURING METHOD FOR SEMICONDUCTOR MODULE
Document Type and Number:
Japanese Patent JP2021057543
Kind Code:
A
Abstract:
To achieve size reduction while reducing inductance.SOLUTION: A semiconductor module (1) includes a first metal wiring board (2) forming a P terminal, a second metal wiring board (3) forming an N terminal, a third metal wiring board (4) forming an output terminal, a first semiconductor element (6) disposed with a collector electrode facing one of main surfaces of the first metal wiring board, and a second semiconductor element (7) disposed with a collector electrode facing one of main surfaces of the third metal wiring board. The second metal wiring board is disposed through an insulating material (A) on one of the main surfaces of the first metal wiring board. The third metal wiring board is disposed with one of the main surfaces facing the first metal wiring board. The first semiconductor element and the second semiconductor element are disposed on the front and back sides so that an emitter electrode (62) of the first semiconductor element is connected to one of the main surfaces of the third metal wiring board and an emitter electrode (72) of the second semiconductor element is connected to one of main surfaces of the second metal wiring board.SELECTED DRAWING: Figure 1
Inventors:
HORI MOTOHITO
IKEDA YOSHINARI
IKEDA YOSHINARI
Application Number:
JP2019181984A
Publication Date:
April 08, 2021
Filing Date:
October 02, 2019
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L25/07; H01L21/52; H01L21/60; H01L25/18; H02M7/48
Domestic Patent References:
| JP2006093733A | 2006-04-06 | |||
| JP2007299781A | 2007-11-15 | |||
| JP2004228403A | 2004-08-12 |
Foreign References:
| WO2014185050A1 | 2014-11-20 |
Attorney, Agent or Firm:
Hiroyoshi Aoki
Amada Masayuki
Yoshimasa Okada
Amada Masayuki
Yoshimasa Okada