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Title:
SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6476497
Kind Code:
A
Abstract:

PURPOSE: To cause recall operation to be a high speed by charging up the node of the FF of a memory cell from a bit side and after that, controlling the activating timing of the FF and the conducting timing of a recall transistor.

CONSTITUTION: Nodes N1 and N2 in a bit line BL side and a bit line -BL side is charged up. Next, the impressing timing of a pair of transistors QR1 and QR2 for recall signals RC1 and RC2 is controlled. Thus, even when a high resistance poly-silicone is used for load resistances R1 and R2, data recall operation from a non-volatile memory cell part 2 to a volatile memory cell part 1 can be executed at the high speed and it is not necessary to change the size of the transistor corresponding to the respective nodes of a flip-flop. Then a transistor forming area on a semiconductor substrate can be reduced.


Inventors:
ARAKAWA HIDEKI
Application Number:
JP23246587A
Publication Date:
March 22, 1989
Filing Date:
September 18, 1987
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C17/00; G11C16/04; (IPC1-7): G11C17/00