PURPOSE: To cause recall operation to be a high speed by charging up the node of the FF of a memory cell from a bit side and after that, controlling the activating timing of the FF and the conducting timing of a recall transistor.

CONSTITUTION: Nodes N1 and N2 in a bit line BL side and a bit line -BL side is charged up. Next, the impressing timing of a pair of transistors QR1 and QR2 for recall signals RC1 and RC2 is controlled. Thus, even when a high resistance poly-silicone is used for load resistances R1 and R2, data recall operation from a non-volatile memory cell part 2 to a volatile memory cell part 1 can be executed at the high speed and it is not necessary to change the size of the transistor corresponding to the respective nodes of a flip-flop. Then a transistor forming area on a semiconductor substrate can be reduced.