SEMICONDUCTOR PACKAGE JIG AND ITS USE METHOD - SUMITOMO METAL ELECTRONICS DEV

Title:

SEMICONDUCTOR PACKAGE JIG AND ITS USE METHOD

Document Type and Number:

Japanese Patent JP2000294666

Kind Code:

A

Abstract:

To accurately set the size between a pair of ceramic substrates of a semiconductor package.

The semiconductor package jig is provided with an internal jig 17 interposed between a pair of ceramic substrates 7, a pair of external jigs 19 in contact with the sides opposite to the internal jig 17 of the pair of ceramic substrates 7, external jig slopes 20 which are formed respectively on the surfaces opposite to the surfaces of the pair of external jigs 19 with which the ceramic substrates 7 are in contact and incline in the direction in which the upper parts approach each other, and a pressing jig 21 having a pair of pressing jig inclined faces 22 which incline in the direction in which the upper parts approach each other and slide with the external jig slopes 20.

Inventors:

NARUSHIGE KEIJI

Application Number:

JP10261099A

Publication Date:

October 20, 2000

Filing Date:

April 09, 1999

Export Citation:

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Assignee:

SUMITOMO METAL ELECTRONICS DEV

International Classes:

H01L23/13; B23K1/19; B23K3/00; H01L23/02; H01L23/06; (IPC1-7): H01L23/02; B23K1/19; B23K3/00; H01L23/06; H01L23/13

Attorney, Agent or Firm:

Hidetake Komatsu (2 outside)

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