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Title:
SEMICONDUCTOR PACKAGE
Document Type and Number:
Japanese Patent JPH11260964
Kind Code:
A
Abstract:

To provide a semiconductor package with high electric reliability, which can raise the reliability on electric connection between each of the terminal of a ceramic substrate and the terminal of a resin wiring board and a bump electrode and the strength of the mechanical connection and can prevent the inferiority of connection, and a semiconductor device.

In a ceramic resin composite semiconductor package, a terminal 13 of a ceramic board 10 and bump electrodes 40 are connected with each other through an alloy junction layers 41. Likewise, the terminals 31 of a resin wiring board 30 and bump electrodes 40 are connected with each other through an alloy junction layer 42. A plated layer 15, on the surface of the terminal 13, and a plated layer 37, on the surface of the terminals 31, are made. The plated layer 15 contains an Ni plated layer 15N, and the plated layer 37 contains an Ni plated layer 37N. The bump electrode 40 is made of Sn-Pb solder paste. The alloy junction layers 41 and 42 are Ni-Sn alloy junction layers.


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Inventors:
YAMAGUCHI HIDEKI
YASUMOTO YASUAKI
Application Number:
JP6361698A
Publication Date:
September 24, 1999
Filing Date:
March 13, 1998
Export Citation:
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Assignee:
TOSHIBA ELECTRONIC ENG
TOSHIBA CORP
International Classes:
H01L23/12; H01L23/14; (IPC1-7): H01L23/12; H01L23/14
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)