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Patent Searching and Data


Title:
SEMICONDUCTOR STATIC MEMORY INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0721779
Kind Code:
A
Abstract:

PURPOSE: To prevent an operational margin and operational speed from being decreased by almost uniformizing and reducing amplitude of an input signal for a sense amplifier, even when the resistance of a bit line is increased.

CONSTITUTION: One bit line BL1 (BL2) is provided with plural load transistors Q11, Q21, Q31 (Q12, Q22, Q32) at prescribed intervals. A load transistor nearest to memory cells (MC1-MCn) in a selecting state is turned on. Thereby, since the distance of a bit line between a connecting point of the load transistor and a connecting point of the memory cell in a selecting state is made short and voltage drop between them is made small, amplitude of an input signal for a sense amplifier is made small and uniformized.


Inventors:
NAKAMURA KAZUYUKI
Application Number:
JP1993000167577
Publication Date:
January 24, 1995
Filing Date:
July 07, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C11/41; G11C11/407; G11C11/417; (IPC1-7): G11C11/417; G11C11/407; G11C11/41
Attorney, Agent or Firm:
京本 直樹 (外2名)