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Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3190496
Kind Code:
B2
Abstract:

PURPOSE: To obtain a high speed FIFO memory.
CONSTITUTION: A write.ring counter 11 successively generates write-in control signals WC1 to WCn and write.transfer gates WG1 to WGn are successively opened by the signals WC1 to WCn. Thus, write data transmitted from an external through a write bit line WBL are successively written into memory cells MC1 to MCn. Moreover, a read.ring counter 12 successively generates read control signals RC1 to RCn. These read control signals RC1 to RCn successively open read-transfer gates RG1 to RGn. Therefore, the data written in the memory cells MC1 to MCn are successively transferred to a read.bit line RBL and outputted to the external as read data.


Inventors:
Sotozono, Hisakazu
Application Number:
JP1993000231871
Publication Date:
July 23, 2001
Filing Date:
September 17, 1993
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
G11C7/00; G06F5/06; (IPC1-7): G11C7/00
Attorney, Agent or Firm:
恩田 博宣