To effectively suppress distortion of an obtained signal waveform at the time of successively reading data stored in a memory means from there with a prescribed time interval, executing D/A conversion to the read data and obtaining the signal waveform.

This circuit is provided with a memory part 11 storing signal data, a latch part 14 for holding time interval data for indicating a data read time interval, a read timing signal generation part 15 for generating read timing signals corresponding to the time interval data from the latch part 14, performing accumulation for the difference from the data read time interval of the cycle of the read timing signals and prolonging the cycle of the read timing signals for one cycle of clock pulse signals when the result of the accumulation exceeds one cycle of the clock pulse signals, a read address signal formation part 16 for reading the signal data from the memory part 11 corresponding to the read timing signals and a D/A conversion part 18 for executing the D/A conversion to the signal data read from the memory part 11 and obtaining signals to be formed.