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Patent Searching and Data


Title:
SIGNAL OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP2017158011
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent a malfunction caused by noise superposed on an output terminal while suppressing expansion of circuit scale and rising of a minimum operation voltage.SOLUTION: A signal output circuit 1 comprises an output circuit 6, a pseudo output circuit 9, a capacitor 12 and a slope control circuit 7. The output circuit 6 includes a transistor 3 and outputs an output signal OUT. The pseudo output circuit 9 is similar to the output circuit 6 at least in partial configuration. The capacitor 12 is connected between input and output nodes N1 and N2 of the pseudo output circuit 9. The slope control circuit 7 charges and discharges the capacitor 12 in accordance with a level of a control signal IN and controls a slope of the output signal OUT by driving the transistor 3 while using a voltage Vc at the node N1. The pseudo output circuit 9 includes a transistor 11 of which the gate is connected to the node N1 and the drain is connected to the node N2, and has the same circuit form as the output circuit 6.SELECTED DRAWING: Figure 1

Inventors:
OKA NORIMASA
KAWAI HIROSHI
Application Number:
JP2016038954A
Publication Date:
September 07, 2017
Filing Date:
March 01, 2016
Export Citation:
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Assignee:
DENSO CORP
International Classes:
H03K17/16; H03K4/94; H03K19/0175
Attorney, Agent or Firm:
特許業務法人 サトー国際特許事務所