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Title:
SYNCHRONISM PROTECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS6053345
Kind Code:
A
Abstract:

PURPOSE: To limit an intermission time of communication by equalizing an absolute passing delay time of each device for active and spare systems, and holding an APC voltage of a phase locked oscillator for reception clock regeneration when a changeover alarm is transmitted to eliminate the need for re-acquisition.

CONSTITUTION: Absolute pass delay times of the active system and the spare system are made equal in each of transmission/reception frequency converters 31, 32, 37 and 38, large power amplifiers 33, 34 and low noise amplifiers 35, 36. When an alarm 85 is transmitted at the switching of active/spare system of each device, an APC voltage of the phase locked oscillator (PLL) of the reception clock regenerator 25 is held. While the said alarm is transmitted, the outputting of a synchronism signal is inhibited, the out of synchronism of frame or burst is prevented at the changeover of the spare/active system of each device to eliminate the need for re-acquisition, the intermission time of communication is reduced and the reliability of communication is increased.


Inventors:
HOTSUTA TOSHIMICHI
SAGA RIYOUKICHI
MITANI TOSHIHIKO
MOROTOMI HITOSHI
HOSHI YOSHITAKA
Application Number:
JP16165283A
Publication Date:
March 27, 1985
Filing Date:
September 02, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04J3/06; H04B1/74; H04B7/15; H04B7/155; H04B7/212; H04J3/00; (IPC1-7): H04B7/155; H04J3/06
Attorney, Agent or Firm:
Uchihara Shin



 
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