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Patent Searching and Data


Title:
TEST CIRCUIT FOR MEMORY TESTER
Document Type and Number:
Japanese Patent JPH0815391
Kind Code:
A
Abstract:

PURPOSE: To constitute a simple circuit for producing a pulse having narrow width equal to the phase difference of clock pulses by regulating only the phase difference of clock pulses while sustaining the pulse width constant thereby inputting clock pulses having phase difference smaller than a predetermined value.

CONSTITUTION: Clock pulses CK1, CK2 of a pulse generation circuit 4 are regulated to have a phase difference ' smaller than the pulse width ΔT and a reset signal is delivered 2 in order to reset D-type FFs 81, 82. At the time of inspection, a circuit 4 receives a pattern data [DPT] and a timing clock 3 and delivers the pulses CK1, CK2, having the phase difference ' and the predetermined pulse width ΔT, sequentially to the terminals CK of the FFs 81, 82. Consequently, the Q terminal of the FF 81 is turned ON while the Q terminal of the FF 82 is turned OFF and a test pulse PTES' is outputted from an ExOR circuit 83. Subsequently, the Q terminal of the FF 82 receiving the pulse CK2 having phase lag ' is turned ON and the circuit 83 stops provision of the pulse PTES'. This circuitry can produce the pulse PTES' having pulse width δt' equal to or narrower than the phase difference ' of the pulses CK1, CK2.


Inventors:
MOTOKI NOBUO
Application Number:
JP1994000164605
Publication Date:
January 19, 1996
Filing Date:
June 23, 1994
Export Citation:
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Assignee:
HITACHI ELECTR ENG
International Classes:
G01R31/3183; G11C29/00; G11C29/56; (IPC1-7): G01R31/3183; G11C29/00
Attorney, Agent or Firm:
梶山 佶是 (外1名)