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Title:
TEST DEVICE FOR INPUT CIRCUIT OF EPLD
Document Type and Number:
Japanese Patent JPH0712899
Kind Code:
A
Abstract:

PURPOSE: To test many input circuits and input structures by taking a test line and an input line formed in the direction of a bit line as a gate, and taking the test line as a drain to be connected to a test circuit formed by EPROM.

CONSTITUTION: Many input circuits 31, 311 in which the data path is determined by a signal controlled by an external pin apply data received by input pins 32-322 to the gate of EPROM transistor of one test line added to an AND memory array 33 in the bit line direction. By this arrangement, all EPROM transistors taking the test line as a drain are erased, and only one pin of many pins 32-322 is operated so that only one circuit 31 is monitored. The condition of the test line is sensed by a sensing circuit 36 connected to a test circuit 34, and output to an input/output pin 38 through an output enable buffer circuit 37. This test is repeatedly made while the configuration of the circuits 31-311, that is, the data path form is changed.


Inventors:
CHIYAN WAN HA
Application Number:
JP1991000249576
Publication Date:
January 17, 1995
Filing Date:
September 27, 1991
Export Citation:
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Assignee:
HYUNDAI ELECTRONICS IND
International Classes:
G01R31/28; G11C29/04; H03K19/177; (IPC1-7): G01R31/28; H03K19/177
Attorney, Agent or Firm:
伊東 忠彦 (外2名)



 
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