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Title:
TEST SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH0261900
Kind Code:
A
Abstract:

PURPOSE: To prevent a test signal from being generated by malfunction hereinafter by generating the test signal by reading out data written on a memory cell based on an external signal, and reloading the data on a memory after completing a test.

CONSTITUTION: 'L' is written on the memory cell 21 as the data. When all of an address signal and a reset signal are set at 'H's in such state, an X decoder 12 and a Y decoder 13 select a word line 24 and a bit line 26. Thereby, transistors 22, 23, and 25 are turned on, and a sense amplifier 27 outputs the 'H' by inverting the output of the memory cell 21, and sets a mode at a test mode via a holding circuit 17. When all of the address signal, a data signal, a write signal, and the reset signal are set at 'H's after the test is completed, the data in the cell 21 is erased, and hereafter, a ROM 22 remains at an off- state even when the 'H' is impressed on its gate, which prevents the mode from entering the test mode. Therefore, it is possible to prevent the test signal from being generated due to the malfunction.


Inventors:
YOSHIKAWA YASUYUKI
Application Number:
JP21345488A
Publication Date:
March 01, 1990
Filing Date:
August 26, 1988
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C17/00; G11C29/00; G11C29/14; H01L21/66; H01L21/822; H01L21/8247; H01L27/04; H01L27/10; H01L29/788; H01L29/792; (IPC1-7): G11C17/00; G11C29/00; H01L21/66; H01L27/04; H01L27/10; H01L29/788; H01L29/792



 
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