Title:
TIME-DIVISION MULTIPLE TIMER AND ITS CONTROL METHOD
Document Type and Number:
Japanese Patent JP3190889
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To surely monitor the time lapse without increasing the scale of a device even if the number of time monitoring to be processed simultaneously increases by providing a second storage means for storing a calculation value when the output of an addition means overflows.
SOLUTION: The data port of a memory 40 is connected to the data port of an adder 50 and a data register 60. The adder 50 reads a memory data signal DMD at an address indicated by a memory address signal DMA from the memory 40 and adds '2' to it for holding. Input and output data controlled by a processor 70 are held by the data register 60. A detection machine 80 inputs an overflow signal outputted by the adder 50 as a timer end signal STE and outputs a read timing signal SRd. An FIFO 90 internally holds a counter address signal DCA when the read timing signal Srd is inputted by fast-in/fast-out operation and outputs a flag signal Frg.
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| JPS58172836 | MULTIPLE STAGE SWITCHING TIMER |
Inventors:
Yuki Holy
Application Number:
JP18962598A
Publication Date:
July 23, 2001
Filing Date:
June 22, 1998
Export Citation:
Assignee:
Miyagi NEC Corporation
International Classes:
G04F3/00; G06F11/30; (IPC1-7): G04F3/00
Domestic Patent References:
| JP63214803A | ||||
| JP6442915A |
Attorney, Agent or Firm:
Shiroyuki Hori