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Title:
TIME-LAG DIGITAL CONVERTER
Document Type and Number:
Japanese Patent JP2013168786
Kind Code:
A
Abstract:

To acquire a digital value with high conversion accuracy without performing calibration or the like on the digital value.

A time-lag digital converter comprises an FET switch 8 which is turned on during a period in which a conversion starting signal is inputted, a constant current source 9 which generates a constant current Ic/N1 and extracts electric charges charging a capacitor 6 when the FET switch 8 is turned on, a comparator 10 which outputs a conversion ending signal when a ramp voltage VP of the capacitor 6 becomes equal to a ground potential, and a counter 12 which counts clock of a term Tclk during a period from input of the conversion starting signal to the output of the conversion ending signal from the comparator 10.


Inventors:
TAKAHASHI TAKANORI
HIRAI AKIHITO
TANIGUCHI EIJI
Application Number:
JP2012000030609
Publication Date:
August 29, 2013
Filing Date:
February 15, 2012
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03M1/50; H03K4/02; H03K5/26
Attorney, Agent or Firm:
田澤 英昭
濱田 初音
久米 輝代
河村 秀央