Title:
TIMING CIRCUIT
Document Type and Number:
Japanese Patent JPH01316044
Kind Code:
A
Abstract:
PURPOSE: To perform the data transmission of DS0 format, having maximum length and phase adjustment over long data transmission and to correct the phase shift of extension transmission line by providing plural timing output devices, etc. CONSTITUTION: A pair of clock input cards 56 and 57 respectively receive compound clock signals 38 and 36 and a DS1 input signal 39, and their outputs 58 and 59 are connected to a stratum 3 clock card 60 and plural timing output cards 61 and 62. Then, the card 61 supplies a compound clock output, and the card 62 supplies a DS1 output. Further, the card 60 locks its phase to a selected input signal and supplies its output 63 to the respective cards 61 and 62. Thus, phase delay at a circuit can be practically eliminated by relocking an input timing signal, in place of amplifying and repeating the input timing signal. Therefore, DS0 format data transmission for the maximum length and phase adjustment over longer data transmission can be performed and the phase shift on the extension transmission line can be corrected.
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Inventors:
TONII UOOREN
SUTEIIBUN JIYONSON
SUTEIIBUN JIYONSON
Application Number:
JP4634589A
Publication Date:
December 20, 1989
Filing Date:
February 27, 1989
Export Citation:
Assignee:
SILICON GENERAL INC
International Classes:
H04J3/06; H04L7/04; H03K5/00; (IPC1-7): H03K5/00; H04L7/04
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)
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