PURPOSE: To provide a circuit of a small scale by contributing an overspecification component to reduction of the circuit scale.

CONSTITUTION: The data received from an input terminal 1 are supplied to the 1st and 2nd input terminals of a computing element 2 through the registers R1-R3. The element 2 adds the input data A and B together to output these added data D and also obtains the data E by multiplying the data C by a coefficient C. Then the element 2 performs the subtraction between both data A and B to output the data F obtained by the subtraction. Then the output data E and F of the element 2 are supplied to the 1st and 2nd input terminals of a computing element 7 through the selectors 3, 5 and 6, a subtractor 4, and the registers R4-R6. The output data E and F of the element 7 are supplied to an adder 11 and a subtractor 12 through the registers R7-R10, a subtractor 8, and the selectors 9, 10 and 13. Then the output data of the subtractor 12 are selected by a selector 14 together with the output data of the adder 11 through the registers R11-R14 and then taken out through an output terminal 15.