PURPOSE: To ensure both the control of the oscillation frequency and compensation of the output level fluctuation by piling the control voltage on the DC bias between the gate and the source of the Schottky barrier or junction type FET and then piling the voltage proportional to the control voltage between the drain and the source.

CONSTITUTION: The DC bias voltage VGS and VDS are applied between the gate and the source plus between the drain and the source of the Shottky barrier or junction type FET in order to actuate oscillator 41. In this case, control voltage ΔV generated from voltage source 46 is piled 47 on DC bias voltage VGS between the gate and the source of FET to control the oscillation frequency. At the same time, voltage K.ΔV proportional to ΔV is piled 48 on DC bias voltage VDS between the drain and the souce. Thus the fluctuation of the output level can be compensated.