Title:
VERY HIGH SPEED FLIP-FLOP
Document Type and Number:
Japanese Patent JP3795479
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a very high speed emitter coupled logic (ECL) flip-flop, and to provide an operating method thereof.
SOLUTION: The ECL flip-flop supplies a clock level for operation of a logic level higher than a data level. Since a clock operates at the logic level higher than that of data such that level shift to occur in the clock is less than level shift in the data, the clock provides a signal of higher definition in comparison with conventional clock signals. The ECL flip-flop can operated in a data rate fairly higher than that of conventional flip-flops.
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Inventors:
Ronald Jay Yepp
Application Number:
JP2003276540A
Publication Date:
July 12, 2006
Filing Date:
July 18, 2003
Export Citation:
Assignee:
NORTHROP GRUMMAN CORPORATION
International Classes:
H03K3/286; H03K19/086; H03K3/2885; H03K3/289; H03K3/012; (IPC1-7): H03K3/286; H03K19/086
Domestic Patent References:
| JP4213911A | ||||
| JP6224738A | ||||
| JP10190440A | ||||
| JP2002026717A |
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko