Title:
積和演算回路及びその方法
Document Type and Number:
Japanese Patent JP4620943
Kind Code:
B2
Abstract:
A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
Inventors:
Osamu Nomura
Takashi Morie
Keisuke Kesaku
Takashi Morie
Keisuke Kesaku
Application Number:
JP2003356625A
Publication Date:
January 26, 2011
Filing Date:
October 16, 2003
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F7/24; G06F17/10; G06F7/38; G06F7/544; G06N3/063
Domestic Patent References:
| JP10187438A | ||||
| JP10240938A | ||||
| JP200315863A | ||||
| JP2201586A | ||||
| JP2000172674A | ||||
| JP4313157A | ||||
| JP6332670A |
Foreign References:
| US5058594 |
Attorney, Agent or Firm:
Takuma Abe
Sogo Kuroiwa
Sogo Kuroiwa