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Title:
ROMセルを含む不揮発性メモリセルのアレイ
Document Type and Number:
Japanese Patent JP6488401
Kind Code:
B2
Abstract:
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Inventors:
Kim, Jinho
Tiwari vipin
Donyan
Russian
Chang Xiao butterfly
Vinin
Yue Caiman
Application Number:
JP2017545283A
Publication Date:
March 20, 2019
Filing Date:
February 05, 2016
Export Citation:
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Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
H01L21/8246; H01L21/336; H01L27/112; H01L27/11521; H01L29/788; H01L29/792
Domestic Patent References:
JP11097653A
JP2012146750A
JP3214770A
JP2016507168A
JP11111935A
Foreign References:
WO2014158677A1
US20140269062
EP0890985A1
US20120175695
US6259132
Attorney, Agent or Firm:
Shinichiro Tanaka
Disciple Maru Ken
▲吉▼田 和彦
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda
Hiroshi Uesugi
Naoki Kondo
Kudo Akira



 
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