PURPOSE: To increase the operating speed sufficiently by controlling a power supply current of a differential amplifier circuit with a clock signal in place of controlling the differential amplifier circuit with a transfer gate.
CONSTITUTION: When a clock CK goes to a high level, a transistor(TR) 33 acts like a current source, an input signal D of a differential amplifier circuit 30a of a master circuit 30 is inversely amplified and outputted to an output terminal Q of the master circuit 30. In this case, a data signal is not propagated but latched in a slave circuit 40. When the clock signal CK goes to a low level, a complementary signal of the clock signal CK goes to a high level, the data signal is inversely amplified by a differential amplifier circuit 40a of the slave circuit 40 and outputted to an output terminal Q of the slave circuit 40. In this case, the data signal is not propagated but latched in the slave circuit 40. Thus, the circuit speed is quickened by a delay time due to a transfer gate.
JP2000269806 | ADDITION SUBTRACTION COUNTER |
JPH02186718 | 1/3 FREQUENCY DIVIDING CIRCUIT |
JPS63117518 | COUNTER |
TOGASHI MINORU
OHATA MASANOBU
SUZUKI MASAO