Title:
方形波出力信号を発生させる集積回路信号発生器
Document Type and Number:
Japanese Patent JP4571122
Kind Code:
B2
Abstract:
A signal generator ( 1 ) for generating a square waveform analog voltage output signal comprises an on-chip DAC ( 12 ) which outputs the analog voltage signal on an output terminal ( 5 ). On-chip first and second programmable registers ( 9,10 ) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit ( 15 ) selectively and alternately switches the first and second registers ( 9,10 ) to an on-chip DAC register ( 17 ) from which the respective first and second digital words are loaded into the DAC ( 12 ) in response to a load DAC signal generated by a control circuit ( 14 ). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal ( 22 ). A flip-flop ( 19 ) in response to the load DAC signal outputs a control signal on a control line ( 25 ) for alternately switching the first and second registers ( 9,10 ) to the DAC register ( 17 ). The frequency of the analog output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.
Inventors:
Donal Pee Gerati
Albert Sea Ogrady
Tudor M Vinurine
Albert Sea Ogrady
Tudor M Vinurine
Application Number:
JP2006502612A
Publication Date:
October 27, 2010
Filing Date:
January 23, 2004
Export Citation:
Assignee:
Analog Devices Inc.
International Classes:
H03K4/02; G06F1/025; G06F1/03; H03M1/66
Domestic Patent References:
| JP1072628U | ||||
| JP5265658A | ||||
| JP8293734A | ||||
| JP7095082A | ||||
| JP2001024441A | ||||
| JP63085210U | ||||
| JP63174721U |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro