Title:
A laminated type semiconductor device and electronic equipment
Document Type and Number:
Japanese Patent JP6184061
Kind Code:
B2
Abstract:
A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability.
Inventors:
Takashi Aoki
Application Number:
JP2012122271A
Publication Date:
August 23, 2017
Filing Date:
May 29, 2012
Export Citation:
Assignee:
Canon Inc
International Classes:
H01L25/10; H01L21/60; H01L25/11; H01L25/18; H05K1/14; H05K3/36
Domestic Patent References:
JP2011086873A | ||||
JP2007103681A | ||||
JP2004047510A | ||||
JP2008218505A | ||||
JP2004128364A | ||||
JP2006156453A | ||||
JP2010062236A | ||||
JP2006086161A | ||||
JP2004289002A |
Attorney, Agent or Firm:
Kazuo Chikajima
Takashi Daejeon
Takashi Daejeon
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