Title:
A nonvolatile memory circuit and a semiconductor device
Document Type and Number:
Japanese Patent JP6103815
Kind Code:
B2
Abstract:
There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.
Inventors:
Masayuki Otsuka
Application Number:
JP2012092458A
Publication Date:
March 29, 2017
Filing Date:
April 13, 2012
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
G11C17/06; G11C17/14; H01L27/10
Domestic Patent References:
JP2008016085A | ||||
JP2005182899A | ||||
JP64079997A |
Foreign References:
WO2012003165A1 | ||||
US20060092742 | ||||
WO2012141118A1 | ||||
US20100061131 |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Hiroshi Fukuda
Kato Kazunori
Hiroshi Fukuda
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