Title:
半導体スタックドパッケージ及びその製造方法
Document Type and Number:
Japanese Patent JP4544784
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor stack, which can reduce the number of working steps and which are other than wire bonding method, by which only insufficient electrical characteristics can be obtained. SOLUTION: This method comprises a step (1) of forming an insulation film 4, a rewiring 5 and posts 9 on the main surface of a first IC chip 1, a step (2) of forming bump electrodes on the main surface of a second IC chip 2, a step (3) of forming a substrate wiring 8 and an aperture 7 on a substrate 3, a step (4) of disposing the IC chip 2 in the aperture 7, so that the main surface of the IC chip 2 is made to face the main surface of the IC chip 1, and a step (5) of making the main surface of the IC chip 2 face the wiring 8 and the main surface of the IC chip 1 and thermocompression-bonding them in batch via an anisotropic conductive film(AFC) 10.
More Like This:
Inventors:
Norio Takahashi
Application Number:
JP2001175523A
Publication Date:
September 15, 2010
Filing Date:
June 11, 2001
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
International Classes:
H01L23/12; H01L25/065; H01L21/60; H01L25/07; H01L25/18
Domestic Patent References:
| JP2000156460A | ||||
| JP200168621A | ||||
| JP2001102410A | ||||
| JP200124149A | ||||
| JP10242381A |
Attorney, Agent or Firm:
Toshiaki Suzuki