PURPOSE: To decrease display data transfer frequency by one-half without increasing numbers of input signals and to reduce power consumption of a signal electrode driving circuit by transferring an inputted display data signal after converting its bit numbers to that of two times.
CONSTITUTION: A clock XSCL for transferring display data is transferred to an input of a clock of a D type flip flop after inverted by an inverter. The D type flip flop outputs an output signal Q which is inverted synchronizing with a trailing edge of XSCL. This signal is made as 2XSCL. Therefore, bit numbers of display data signals can be made as that of two times and transfer frequency can be decreased by one-half by making display data signals D1, D3, Q2, Q4 as input data of an IC for driving electrodes of the odd number signals, display data signals DO, D2, Q1, Q3 as input data of an IC for driving electrodes of the even numbers signals, and using 2XSCL as a clock for display data signals of a both signals electrodes driving circuit.