[0001] This application claims the benefit of US Provisional Patent Application No. 63/145,225, filed 3 February 2021, the entire contents of which is incorporated herein by reference.

BACKGROUND

[0002] A device may include multiple on-board chargers that are each capable of charging one or more power sources (e.g., batteries) of the device using power received from an external source. The on-board chargers may include a main charger and a secondary charger, each with different characteristics. Depending on charging context, a controller of the device may utilize the main charger or the secondary charger to charge the one or more power sources using the power received from the external source.

BRIEF SUMMARY

[0003] Battery charging on mobile devices may be thermally constrained. As such, converter efficiency may be an important metric for the battery management system. The Universal Serial Bus (USB) standard defines two modes: a power delivery (PD) mode, and a programmable power supply (PPS) mode. In the PD mode, a source device may output a power signal with a fixed voltage and current allocation to a sink device, which may perform regulation of voltage and current. In the PPS mode, a source device may output a power signal with a regulated voltage and current to a sink device, which may use the power signal with no or minimal regulation. Some sink devices include both a 3-Level buck regulator and an open loop charge pumped divider. The 3-Level buck regulator may be used by the sink device when operating under a PD mode (e.g., to perform voltage and/or current regulation), while the open loop charge pumped divider may be used by the sink device when operating under the PPS mode (e.g., to perform a voltage division operation, such as Vin/2).

[0004] In accordance with one or more aspects of this disclosure, a 3-Level buck regulator of a sink device may be operated to perform a voltage division operation. As one example, when receiving a power signal from a source device operating under a PPS mode, a controller of the sink device may operate the 3-Level buck regulator of the sink device to perform a voltage division operation. For instance, the controller may operate the 3-Level buck regulator to divide a voltage of the power signal by two (e g., Vin/2). As another example, when receiving a power signal from a source device operating under a PD mode, the controller of the sink device may operate the 3-Level buck regulator to regulate a voltage and/or current level of the power signal. In this way, the sink device may use common hardware regardless of whether the source device is operating in the PD or PPS mode.

[0005] In one example, a method includes receiving, by a sink device and from a power adapter, an input power signal having an input voltage level; and performing, by hardware of a 3-Level buck converter of the sink device, a divide by two operation on the input power signal to generate an output power signal having a voltage level that is half of the input voltage level.

[0006] Additional features, advantages, and embodiments of the disclosed subject matter may be set forth or apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood both the foregoing summary and the following detailed description are illustrative and are intended to provide further explanation without limiting the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. l is a block diagram illustrating an example of a system that includes a mobile device and a power adapter in accordance with various aspects of this disclosure.

[0008] FIGS. 2A-2D are graphs illustrating example signals of a 3-Level buck operated as a DIV2 regulator, in accordance with one or more aspects this disclosure.

[0009] FIGS. 3A and 3B are graphs illustrating example current levels flowing through an inductor of a 3-Level buck, in accordance with one or more aspects this disclosure.

[0010] FIG. 4 is a block diagram illustrating an example of processing circuitry that may generate control signals for switches of a 3-Level buck converter, in accordance with one or more aspects of this disclosure.

[0011] FIG. 5 is a flow diagram illustrating an example technique for operating a 3-Level buck, in accordance with one or more aspects of this disclosure.

DETAILED DESCRIPTION

[0012] FIG. 1 is a block diagram illustrating an example of a system 100 that includes a mobile device 102 and a power adapter 110, in accordance with various aspects of this disclosure. Power adapter 110 may be an AC adapter, AC/DC adapter, or AC/DC converter. Power adapter 110 may be a type of external power supply, enclosed in a case (e.g., an AC plug). Power adapter 110 may also be a plug pack, plug-in adapter, adapter block, domestic mains adapter, line power adapter, wall wart, power brick, and power adapter. Power adapter 110 may contain a transformer to convert the mains electricity voltage to a lower voltage. As shown in FIG. 1 , power adapter 110 may output a direct current (DC) power signal to mobile device 102 having voltage level VBUS N and current level I BUS IN.

[0013] Power adapter 110 may operate in a variety of modes and/or in accordance with a variety of standards. For example, where power adapter 110 is configured to operate in accordance with a Universal Serial Bus (USB) standard, power adapter 110 may operate in a PD mode or a PPS mode. When operating in the PD mode, power adapter 110 may output a power signal with a voltage level from a limited set of voltage levels (e.g., 5 V, 9 V, 15 V or 20 V). When operating in the PPS mode, power adapter 110 may output a regulated power signal with programmable voltage and current levels (e.g., at a higher resolution/granularity than the PD mode).

[0014] Mobile device 102 may represent any device that includes a power storage device capable of being recharged by an external power adapter, such as power adapter 110. Examples of mobile device 102 include, but are not limited to, a mobile phone (including a so-called “smartphone”), smart glasses, a smart watch, a portable speaker (including a portable smart speaker), a laptop computer, a portable gaming system, a wireless gaming system controller, and the like. In some examples, mobile device 102 may be a foldable device in that components of mobile device 102 may be distributed across two housings joined by a hinge. As shown in the example of FIG. 1, mobile device 102 may include charger 112, processing circuitry 108, and power storage device 124.

[0015] Processing circuitry 108 may represent circuitry configured to support operation of mobile device 102 and may execute software (or, in other words, a set of instructions) that may enable execution of hierarchical software layers to present various functionalities for use by a user. Processing circuitry 108 may, for example, execute a kernel forming a base layer by which an operating system may interface with various other processing units, such as a camera, microphones, sensors, etc. Processing circuitry 108 may also execute the operating system which presents an application space in which one or more applications (e.g., first party and/or third-party applications) may execute to present graphical user interfaces with which to interact with the user.

[0016] Processing circuitry 108 may include one or more of a microprocessor, a controller, a digital signal processor (DSP), an accelerated processing unit (APU), an application processor (AP), a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or equivalent discrete or integrated logic circuitry. The functions attributed to processing circuitry 108 in this disclosure may be embodied as software (as noted above), firmware, hardware and combinations thereof. Although example mobile device 102 of FIG. 1 is illustrated as including one processing circuitry 108, other example mobile devices according to this disclosure may include multiple processors (or multiple so-called “cores,” which is another way to refer to processors when packaged together) configured to execute one or more functions attributed to processing circuitry 108 of mobile device 102 individually or in different cooperative combinations.

[0017] Power storage device 124 may be configured to store electrical energy for use by components of mobile device 102. Examples of power storage device 124 include batteries, such as secondary cell rechargeable batteries, and the like. Some examples of batteries include a lithium-ion battery, a nickel-cadmium battery, or any other type of rechargeable battery such as nickel-metal hydride, lead acid or lithium-ion polymer. In some examples, power storage device 124 may represent an array of power storage devices. For instance, where mobile device 102 is a foldable device, power storage device 124 may include a first battery in a first housing of the foldable device and a second battery in a second housing of the foldable device.

[0018] Main charger 112 may represent a circuit configured to generate a power signal to charge power storage device 124 and/or provide power to other components of mobile device 102. As shown in the example of FIG. 1, main charger 112 may be a 3-Level buck converter that include four switches (Q1-Q4), flying capacitor CFLY, output inductor L, and output capacitor Cour. Each of the switches may represent any component capable of selectively conducting electrical energy. Examples of switches include, but are not limited to, fieldeffect transistors (FETs) such as metal oxide FETs (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistor (IGBT), any other type of transistor, or any other type of switch.

[0019] Operation of the switches may be controlled by a controller, such as processing circuitry 108. For instance, where power adapter 110 is operating in a PD mode, processing circuitry 108 may operate the switches such that main charger 112 outputs a regulated power signal to power storage device 124. As one example, to output the regulated power signal, processing circuitry 108 may operate the switches in four stages:

[0020] In a first stage, processing circuitry 108 may turn on QI and Q4 (e.g., close QI and Q4), presenting VIN minus VFLY— in other words, V IN over 2 - at the switch node (SN). At the same time, the CFLY capacitor gets charged while the inductor L gets energized, because the output is lower than the switch node voltage. [0021] In a second stage, processing circuitry 108 may turn off QI and turn on Q2, bringing the switch node to ground. This leaves CFLY capacitor disconnected, and de-energizes the inductor L.

[0022] In a third stage, processing circuitry 108 turns off Q4 and turns on Q3, connecting the CFLY capacitor directly across the switch node. This has the effect of discharging the capacitor voltage, and energizing the inductor current.

[0023] In a fourth stage, processing circuitry 108 turns off Q3 and turns Q4 back on, connecting the switch node directly to ground. This leaves the CFLY capacitor disconnected, and de-energizes the inductor L once again in preparation for the next cycle.

[0024] As the input voltage decreases, processing circuitry 108 may automatically increase the duration of stages 1 and 3— in other words, increases the duty cycle— in order to maintain a regulated output voltage. This has the effect of reducing the inductor current ripple until a minimum is reached when the input is exactly equal to twice the output. At this point, the switch-node remains at VIN over 2 all the time, while processing circuitry 108 changes between stage 1 and stage 3 in order to charge and discharge the flying capacitor each cycle. As the input voltage continues to decrease, processing circuitry 108 may continue to increase the duty cycle, until QI and Q3 are turned on during the same time period. In this case, the switch node starts alternating between VIN and VI over 2.

[0025] As such, when power adapter is operating in the PD mode, QI and Q2 may be buck modulator loop controlled, and Q3 and Q4 may be capacitor voltage regulation loop controlled. Therefore, the voltage across the CFLY capacitor, the output voltage Vo, and the load current Io can be regulated. However, as shown in FIG. 3A, this arrangement may produce significant current ripple in inductor L.

[0026] As noted above, when operating in the PPS mode, power adapter 110 may output a power signal to mobile device 102 with a regulated voltage level and a regulated current level. Though no further regulation of the power signal may be required, it may be desirable to convert the input power signal into an output power signal with half the voltage and twice the current (e.g., VO=VBUS IN/2 and ILOAD=2*IBUS_IN). TO this end, in some example, mobile device 102 may include a 2:1 switch-capacitor power converter. However, including this additional hardware may not be desirable.

[0027] In accordance with one or more aspects of this disclosure, when power adapter 110 is operating in the PPS mode, processing circuitry 108 may control switches of main charger 112 such that main charger 112 converts the input power signal into an output power signal with half the voltage and twice the current. For instance, processing circuitry 108 may modify the charge balancing loop otherwise used to control the inner switches (e.g., Q3 and Q4) to modulate the outer switches (e.g., QI and Q2) in an anti-phase manner. As one example, in a first phase QI and Q4 may be on while Q2 and Q3 may be off, and in a second phase Q2 and Q3 may be on while QI and Q4 may be off. This enables processing circuitry 108 to only regulate the flying capacitor voltage to Vin/2 (e g., by adjusting a ratio of the two phases) which means the VSW ripple is minimized and thus the inductor L may experience no significant RMS AC voltage (e.g., thereby minimizing the core losses). In this way, main charger 112 can operate as if it was an inductorless DIV2 regulator with very high efficiency. [0028] As such, when power adapter is operating in the PPS mode, Q3 and Q4 may be capacitor voltage regulation loop controlled, and QI and Q2 may be inverse capacitor voltage regulation loop controlled. Therefore, when power adapter is operating in the PPS mode, the voltage across the CFLY capacitor can be directly regulated at mobile device 102 (e.g., regulation of voltage and current may be offloaded to power adapter 110). The duty cycle of the switches may be non 50%. As shown in FIG. 3B, this arrangement may minimize current ripple in inductor L (e.g., which may minimize alternating current resistance (ACR) losses). [0029] FIGS. 2A-2D are graphs illustrating example signals of a 3-Level buck operated as a DIV2 regulator, in accordance with one or more aspects this disclosure. FIG. 2A illustrates example current levels flowing through an inductor, such as inductor L of main charger 112. FIG. 2B illustrates example input and output voltages of a charger, such as main charger 112 of FIG. 1. As shown, in the example of FIG. 2B, main charger 112 may convert an input voltage of 9 volts to an output volage of 4.5 volts. FIG. 2C illustrates example power dissipation and efficiency levels of a charger, such as main charger 112 of FIG. 1. As shown, in the example of FIG. 2C, an efficiency level of 95% may be achieved with a power dissipation level of 1.5W. FIG. 2D illustrates example Vsw.

[0030] FIGS. 3A and 3B are graphs illustrating example current levels flowing through an inductor of a 3-Level buck, in accordance with one or more aspects this disclosure. FIG. 3 A illustrates examples current levels flowing through inductor L of main charger 112 when main charger 112 is operating as a 3-Level buck regulator (e.g., when power adapter 110 is operating in the PD mode). FIG. 3B illustrates examples current levels flowing through inductor L of main charger 112 when main charger 112 is operating as a DIV2 regulator (e.g., when power adapter 110 is operating in the PPS mode).

[0031] FIG. 4 is a block diagram illustrating an example of processing circuitry that may generate control signals for switches of a 3-Level buck converter, in accordance with one or more aspects of this disclosure. Processing circuitry 408 of FIG. 4 may be an example of processing circuitry 108 of FIG. 1. As shown in FIG. 4, processing circuitry 408 may include buck modulator 424, charge balance modulator 426, and mode select unit 428.

[0032] Buck modulator 424 may be configured to generate control signals for switches QI and Q2 of main charger 112 of FIG. 1. For instance, buck modulator 424 may generate a control signal BUCK_DUTY. As shown in FIG. 1, buck modulator 424 may generate the control signal BUCK_DUTY based on various parameters, such as an input current IIN, a target output current IOUT, and a target output voltage VOUT.

[0033] Charge balance modulator 426 may be configured to generate control signals for at least switches Q3 and Q4 of main charger 112 of FIG. 1. For instance, charge balance modulator 426 may generate a control signal CHARGE BALANCE DUTY to at least control switches Q3 and Q4. As shown in FIG. 1, charge balance modulator 426 may generate the control signal CHARGE BALANCE DUTY based on various parameters, such as an input voltage VIN, and a voltage across flying capacitor CFLY VCFLY.

[0034] Mode select unit 428 may selectively change which control signals are received by switches of main charger 112 based on an operating mode. For instance, where main charger 112 is to perform a divide by two operation (e.g., responsive to determining that power adapter 110 is operating in a PPS mode), mode select unit 428 may pass control signal CHARGE BALANCE DUTY to QI and Q2. By contrast, where charger 112 is to perform active regulation (e.g., responsive to determining that power adapter 110 is operating in a PD mode), mode select unit 428 may pass control signal BUCK DUTY to QI and Q2.

[0035] As one specific example, processing circuitry 408 may pass control signals to switches Q1-Q4 (e.g., to gates of the switches) in accordance with the following table (where BUCK is the BUCK DUTY control signal, CB is the CHARGE BALANCE DUTY control signal, and _N after a control signal denotes a logical not of the control signal). [0036] FIG. 5 is a flow diagram illustrating an example technique for operating a 3-Level buck, in accordance with one or more aspects of this disclosure. For purposes of explanation, the technique of FIG. 5 is described with reference to system 100 of FIG 1.

[0037] As discussed above, the operation of main charger 112 of mobile device 102 of system 100 may be varied based on an operating mode of power adapter 110 of system 100. Mobile device 102 may determine whether power adapter 110 is operating in a programable power supply (PPS) mode or a power delivery (PD) mode (e.g., of the Universal Serial Bus (USB) standard) (502).

[0038] Where power adapter 110 is operating in the PPS mode (e g., responsive to determining that power adapter 110 is operating in, or is capable of operating in, the PPS mode), main charger 112 may output, to power adapter 110, a requested voltage level and a requested current level (504). For instance, processing circuitry 108 of mobile device 102 may output a message (e g., in accordance with signaling described in the USB Standard) to power adapter 110 that include a request for a power signal at 9 volts and 1.5 amps. In some examples, mobile device 102 may periodically (e.g., every 10 seconds) output a message with updated requested voltage/current levels.

[0039] Mobile device 102 may receive, from power adapter 110, an input power signal having the requested voltage level and the requested current level (506). For instance, mobile device may receive a power signal having voltage level VBUS _IN and current level IBUS IN. [0040] Mobile device 102 may perform, using hardware of a 3-Level buck converter, a divide by two operation to generate an output power signal (508). For instance, processing circuitry 108 may control operation of the switches of main charger 112 to perform the divide by two (DIV2) operation. In some examples, to perform the divide by two operation, processing circuitry 108 may operate the switches of main charger 112 in two phases. For instance, in a first phase of the two phases, processing circuitry 108 may turn on first switch QI and fourth switch Q4, and turn off second switch Q2 and third switch Q3. In a second phase of the two phases, processing circuitry 108 may turn off first switch QI and fourth switch Q4, and turn on second switch Q2 and third switch Q3. Processing circuitry 108 may alternate between the two phases and adjust a duty cycle of the two phases to maintain a voltage across a flying capacitor (e.g., CFLY) at half of the input voltage level (e.g., such that V CFLY=VIN/2.

[0041] Where power adapter 110 is operating in the PD mode (e.g., responsive to determining that power adapter 110 is operating in the PD mode, or responsive to determining that power adapter 110 is not capable of operating in the PPS mode), mobile device 102 may receive, from power adapter 110, an input power signal having a voltage level (512). For instance, mobile device may receive a power signal having voltage level VBUS IN and current level IBUS IN. AS noted above, in such scenarios, the voltage level of the input signal may not be finely adjustable such that any voltage regulation may be performed onboard mobile device 102.

[0042] Mobile device 102 may perform, using hardware of a 3 -Level buck converter, regulation to generate an output power signal (514). For instance, processing circuitry 108 may control operation of the switches of main charger 112 to perform the regulation using the four phase process described above. By performing the regulation using the four phase process, main charger 112 may finely regulate the voltage level and the current level of the output power signal.

[0043] Regardless of whether the output power signal was generated (e.g., via the DIV2 operation or the onboard regulation), main device 102 may charge a battery with the output power signal (510). For instance, main charger 112 may provide the output power signal to power storage device 124.

[0044] The techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more processors, including one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, as well as any combinations of such components. The term “processor” or “processing circuitry” may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. A control unit including hardware may also perform one or more of the techniques of this disclosure.

[0045] Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various techniques described in this disclosure. In addition, any of the described units, modules or components may be implemented together or separately as discrete but interoperable logic devices. Depiction of different features as modules or units is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be realized by separate hardware, firmware, or software components. Rather, functionality associated with one or more modules or units may be performed by separate hardware, firmware, or software components, or integrated within common or separate hardware, firmware, or software components. [0046] The techniques described in this disclosure may also be embodied or encoded in an article of manufacture including a computer-readable storage medium encoded with instructions Instructions embedded or encoded in an article of manufacture including a computer-readable storage medium encoded, may cause one or more programmable processors, or other processors, to implement one or more of the techniques described herein, such as when instructions included or encoded in the computer-readable storage medium are executed by the one or more processors. Computer readable storage media may include random access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), flash memory, a hard disk, a compact disc ROM (CD-ROM), a floppy disk, a cassette, magnetic media, optical media, or other computer readable media. In some examples, an article of manufacture may include one or more computer-readable storage media.

[0047] In some examples, a computer-readable storage medium may include a non-transitory medium. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. In certain examples, a non-transitory storage medium may store data that can, over time, change (e g., in RAM or cache).