USING RF INTERPOLATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/032,606, entitled, “6-PHASE DIGITALLY ASSISTED TX/RX HARMONIC USING RF INTERPOLATION,” filed May 30, 2020 by Al-Qaq et al. , which is incorporated by reference in its entirety.

FIELD

[0002] This disclosure generally relates to architectures for reducing unwanted harmonic content in transceivers.

BACKGROUND

[0003] In a wireless terminal, such as a cellular phone, it is common to have the undesired local oscillator clock generated harmonic signals (harmonics) that may interfere with signal processing. On the transmitter side, these harmonics can be mixed back to near to the carrier frequency of the desired signal through non-linearity and create near channel distortion and may impact other wireless terminals nearby using carrier frequencies that are the same or close to the same. On the receiver side, a blocker signal that is near the desired signal’s clock harmonics’ frequency can, when mixed back to baseband frequency, fall on top of the desired signal frequency through the down-conversion process to degrade the signal-to-noise and distortion ratio for the received signal. It is desirable to reduce the impact of these clock harmonics as much as possible. SUMMARY

[0004] According to one aspect of the present disclosure, a transmitter includes an in-phase/quadrature (IQ) signal source, a frequency synthesizer, and a harmonic rejection mixer. The (IQ) signal source is configured to receive a first IQ signal and generate therefrom a second IQ signal, the second IQ signal being in a differential format having an in-phase component, a quadrature component, an inverse of the in- phase component, and an inverse of the quadrature component, with one or both of the in-phase and quadrature components of the second IQ signal being a linear combination of the in-phase component and quadrature component of the first IQ signal. The frequency synthesizer is configured to generate a 6-phase clock signal including a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%. The harmonic rejection mixer includes a first mixing section having: a first set of mixers, each configured to receive a corresponding one of the first set of clock signals, a first of the first set of mixers further configured to receive the in-phase component of the second IQ signal, and a second of the first set of mixers further configured to receive the inverse of the quadrature component of the second IQ signal; and a second set of mixers, each configured to receive a corresponding one of the second set of clock signals, a first of the second set of mixers further configured to receive the quadrature component of the second IQ signal, and a second of the second set of mixers further configured to receive the inverse of the in-phase component of the second IQ signal. The harmonic rejection mixer is configured to: form a first intermediate signal by combining an output of each of the first set of mixers, form a second intermediate signal by combining an output of each of the second set of mixers, and combine the first and second intermediate signals to form a first output signal for the harmonic rejection mixer.

[0005] Optionally, in the preceding aspect, a third of the of the first set of mixers is further configured to have an input connected to ground; and a third of the of the second set of mixers is further configured to have an input connected to ground. [0006] Optionally, in the first aspect above, a third of the of the first set of mixers is further configured to have an input connected to ground; and a third of the of the second set of mixers is further configured to have an input connected to ground.

[0007] Optionally, in the preceding aspect, the first mixing section further includes: a third set of mixers, each configured to receive a corresponding one of the first set of clock signals and one of the components of the second IQ signal; and a fourth set of mixers, each configured to receive a corresponding one of the second set of clock signals and one of the components of the second IQ signal. The harmonic rejection mixer is further configured to: form a third intermediate signal by combining an output of each of the third set of mixers, form a fourth intermediate signal by combining an output of each of the fourth set of mixers, and further combine the third and fourth intermediate signals with the first and second intermediate signals to form a first output signal for the harmonic rejection mixer.

[0008] Optionally, in any of the preceding aspects, the transmitter further comprises a first and a second variable gain amplifier. The first variable gain amplifier is configured to: receive the first intermediate signal; and amplify the first intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer. The second variable gain amplifier configured to: receive the second intermediate signal; and amplify the second intermediate signal prior to combining the first and second intermediate signals to form the first output signal for the harmonic rejection mixer.

[0009] Optionally, in any of the preceding aspects, the harmonic rejection mixer further comprises a second mixing section, including: a third set of mixers, each configured to receive a corresponding one of the first set of clock signals, a first of the first set of mixers further configured to receive the inverse of the in-phase component of the second IQ signal, and a second of the first set of mixers further configured to receive the quadrature component of the second IQ signal; and a fourth set of mixers, each configured to receive a corresponding one of the second set of clock signals, a first of the second set of mixers further configured to receive the inverse of the quadrature component of the second IQ signal, and a second of the second set of mixers further configured to receive the in-phase component of the second IQ signal. The harmonic rejection mixer is configured to: form a third intermediate signal by combining an output of each of the third set of mixers, form a fourth intermediate signal by combining an output of each of the fourth set of mixers, and combine the third and fourth intermediate signals to form a second output signal for the harmonic rejection mixer.

[0010] Optionally, in the preceding aspect, the transmitter further comprises an inductive coupler, including: a first coil configured to receive the first output signal for the harmonic rejection mixer at a first terminal and the second output signal for the harmonic rejection mixer at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single ended output for the transmitter and a second terminal connected to ground.

[0011] Optionally, in the preceding aspect, the transmitter further comprises a power amplifier configured to receive and amplify the single ended output.

[0012] Optionally, in the preceding aspect, the transmitter further comprises an antenna configured to receive and transmit the single ended output.

[0013] Optionally, in any of the preceding aspects, the frequency synthesizer is configured to generate a 6-phase clock signal by generating the first set of clock signals from a voltage controller oscillator and generate the second set of clock signals from the first set of clock signals by introducing a phase shift to the first set of clock signals.

[0014] Optionally, in any of the preceding aspects, the IQ signal source comprises: a digital correction circuit configured to receive the first IQ signal in digital format and generate therefrom the second IQ signal in digital format; a first digital to analog converter configured to receive the in-phase component of the second IQ signal in digital format and generate therefrom the in-phase component of the second IQ signal in a differential, analog format; and a second digital to analog converter configured to receive the quadrature component of the second IQ signal in digital format and generate therefrom quadrature component of the second IQ signal in a differential, analog format. [0015] According to another aspect of the present disclosure, there is provided a method of transmitting a signal, including: receiving a first in-phase/quadrature (IQ) signal; and generating a second IQ signal from the first IQ signal, the second IQ signal being in a differential format having an in-phase component, a quadrature component, an inverse of the in-phase component, and an inverse of the quadrature component, with one or both of the in-phase and quadrature components of the second IQ signal a being a linear combination of the in-phase component and quadrature component of the first IQ signal. The method also includes: receiving a 6-phase clock signal including a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%; and generating a first output signal from the second IQ signal and the 6-phase clock signal. The first output signal is generated by: receiving at each of a first set of mixers a corresponding one of the first set of clock signals, receiving at a first of the first set of mixers the in-phase component of the second IQ signal; receiving at a second of the second set of mixers the inverse of the quadrature component of the second IQ signal; combining an output of each of the first set of mixers to form a first intermediate signal; receiving at each of a second set of mixers a corresponding one of the second set of clock signals, receiving at a first of the second set of mixers the inverse of the in-phase component of the second IQ signal; receiving at a second of the second set of mixers the quadrature component of the second IQ signal; combining an output of each of the second set of mixers to form a second intermediate signal; and generating the first output signal by combining the first intermediate signal and the second intermediate signal.

[0016] Optionally, in the preceding aspect, the first output signal is further generated from the second IQ signal and the 6-phase clock signal by: connecting an input of a third of the of the first set of mixers to ground; and connecting an input of a third of the of the second set of mixers to ground.

[0017] Optionally, in the first aspect above of a method of transmitting a signal, the first output signal is further generated from the second IQ signal and the 6-phase clock signal by: receiving at a third of the of the first set of mixers a component of the second IQ signal other than the in-phase component and the inverse of the quadrature component, and receiving at a third of the of the second set of mixers a component of the second IQ signal other than the quadrature component and the inverse of the in- phase component.

[0018] Optionally, in the preceding aspect, the first output signal is further generated from the second IQ signal and the 6-phase clock signal by: receiving at each of a third set of mixers a corresponding one of the first set of clock signals and one of the components of the second IQ signal, combining an output of each of the third set of mixers to form a third intermediate signal; receiving at each of a fourth set of mixers a corresponding one of the second set of clock signals and one of the components of the second IQ signal; and combining an output of each of the fourth set of mixers to form a fourth intermediate signal, wherein generating the first output signal by further combining the third intermediate signal and the fourth intermediate signal the first intermediate signal and the second intermediate signal.

[0019] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises individually amplifying the first intermediate signal and the second intermediate signal prior to combining the first intermediate signal and the second intermediate signal to generate the first output signal.

[0020] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises generating a second output signal from the second IQ signal and the 6-phase clock signal by: receiving at each of a third set of mixers a corresponding one of the first set of clock signals, receiving at a first of the third set of mixers the inverse of the in-phase component of the second IQ signal,, receiving at a second of the second set of mixers the quadrature component of the second IQ signal, combining an output of each of the third set of mixers to form a third intermediate signal, receiving at each of a fourth set of mixers a corresponding one of the second set of clock signals, receiving at a first of the fourth set of mixers the in- phase component of the second IQ signal, receiving at a second of the fourth set of mixers the inverse of the quadrature component of the second IQ signal, combining an output of each of the fourth set of mixers to form a fourth intermediate signal, and generating the second output signal by combining the third intermediate signal and the fourth intermediate signal. [0021] Optionally, in the preceding aspect, the method further comprises applying the first output signal and the second output signal to a first terminal and a second terminal, respectively, of a first coil of an inductive coupler; receiving and amplifying an output from a second coil of the inductive coupler that is inductively coupled to the first coil; and transmitting the amplified output.

[0022] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises generating the 6-phase clock signal by: generating the first set of clock signals from a voltage controller oscillator, and generating the second set of clock signals from the first set of clock signals by introducing a phase shift to the first set of clock signals.

[0023] Optionally, in any of the preceding aspects of a method of transmitting a signal, the method further comprises: receiving the first IQ signal in digital format; generating the second IQ signal in digital format from the first IQ signal in digital format; generating from the in-phase component of the second IQ signal in digital format the in-phase component of the second IQ signal in a differential, analog format; and generating from the quadrature component of the second IQ signal in digital format the in-phase component of the second IQ signal in a differential, analog format.

[0024] According to an additional aspect of the present disclosure, a receiver includes: a frequency synthesizer configured to generate a 6-phase clock signal including a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%; a harmonic rejection mixer; and a correction circuit. The harmonic rejection mixer comprises a first mixing section, including: a first set of mixers, each configured to receive and mix one of the first set of clock signals and an input signal to generate, in a first of the first set of mixers, an in-phase component of a differential in-phase/quadrature (IQ) signal and, in a second of the first set of mixers, an inverse of a quadrature component of the differential IQ signal; and a second set of mixers, each configured to receive and mix one of the second set of clock signals and the input signal to generate, in a first of the second set of mixers, the quadrature component of the differential IQ signal and, in a second of the second set of mixers, an inverse of the in-phase component of the differential IQ signa. The correction circuit is configured to receive the components of the differential IQ signal and generate therefrom a baseband IQ signal, with one or both of the in-phase and quadrature components of the baseband IQ signal being a linear combination of components of the differential IQ signal.

[0025] Optionally, in the preceding aspect a third of the of the first set of mixers is further configured to have an output connected to ground; and a third of the of the second set of mixers is further configured to have an output connected to ground.

[0026] Optionally, in the first aspect above for a receiver, a third of the of the first set of mixers is further configured to generate a component of the differential IQ signal other than the in-phase component and the inverse of the quadrature component; and a third of the of the second set of mixers is further configured to generate a component of the differential IQ signal other than the quadrature component and the inverse of the in-phase component.

[0027] Optionally, in any of the preceding aspects for a receiver, the receiver also includes: one or more low noise amplifiers configured to: receive and amplify the input signal; and supply the amplified input signal to the harmonic rejection mixer.

[0028] Optionally, in the preceding aspect, the one or more low noise amplifiers are configured to provide the amplified input signal as a differential output, the first mixing section receiving a positive side output of the low noise low noise amplifiers. The harmonic rejection mixer further comprises a second mixing section, including: a first third of three mixers, each configured to receive and mix one of the first set of clock signals and a negative side output of the low noise low noise amplifiers to generate, in a first of the first set of mixers, the inverse of the in-phase component of the differential IQ signal and, in a second of the first set of mixers, the quadrature component of the differential IQ signal; and a second set of mixers, each configured to receive and mix one of the second set of clock signals and a negative side output of the low noise low noise amplifiers to generate, in a first of the second set of mixers, the inverse of the quadrature component of the differential IQ signal and, in a second of the second set of mixers, the in-phase component of the differential IQ signal. [0029] Optionally, in any of the preceding two aspects for a receiver, the receiver also includes an antenna configured to receive and supply the input signal to the one or more low noise amplifiers.

[0030] Optionally, in any of the preceding aspects for a receiver, the frequency synthesizer is configured to generate a 6-phase clock signal by generating the first set of clock signals from a voltage controller oscillator and generate the second set of clock signals from the first set of clock signals by introducing a phase shift to the first set of clock signals.

[0031] Optionally, in any of the preceding aspects for a receiver, the correction circuit comprises: a first analog to digital converter configured to receive the in-phase components of the differential IQ signal in an analog format and generate therefrom an in-phase component of an input IQ signal in digital format; a second analog to digital converter configured to receive the quadrature components of the differential IQ signal in an analog format and generate therefrom a quadrature component of an input IQ signal in digital format; and a digital correction circuit configured to receive the input IQ signal in digital format and generate therefrom the baseband IQ signal.

[0032] According to another aspect of the present disclosure, there is provided a method of receiving a signal that includes: receiving an input signal; receiving a 6- phase clock signal including a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%; and generating a baseband IQ signal from the input signal. Generating the baseband IQ signal includes: receiving at each of a first set of mixers a corresponding one of the first set of clock signals and the input signal, generating in a first of the first set of mixers an in-phase component of a differential in phase/quadrature (IQ) signal, generating in a second of the first set of mixers an inverse of a quadrature component of the differential IQ signal, receiving at each of a second set of mixers a corresponding one of the second set of clock signals and the input signal, generating in a first of the second set of mixers the quadrature component of the differential IQ signal, generating in a second of the second set of mixers the quadrature component of the differential IQ signal, and generating from the components of the differential IQ signal a baseband IQ signal, with one or both of the in-phase and quadrature components of the baseband IQ signal being a linear combination of components of the differential IQ signal.

[0033] Optionally, in the preceding aspect, the baseband IQ signal is further generated by: setting the output of a third of the first set of mixers to ground; and setting the output of a third of the second set of mixers to ground.

[0034] Optionally, in the first aspect above of a method of receiving a signal, the baseband IQ signal is further generated by: generating in a third of the first set of mixers component of the differential IQ signal other than the in-phase component and the inverse of the quadrature component; and generating in a third of the second set of mixers component of the differential IQ signal other than the quadrature component and the inverse of the in-phase component.

[0035] Optionally, in the preceding aspect, the baseband IQ signal is further generated by: receiving at each of a third set of mixers a corresponding one of the first set of clock signals and the input signal, generating in each mixer of the third set a component of a component of the differential IQ signal, receiving at each of a fourth set of mixers a corresponding one of the second set of clock signals and the input signal, and generating in each mixer of the fourth set a component of a component of the differential IQ signal.

[0036] Optionally, in any of the preceding aspects of a method of receiving a signal, the method further comprises: amplifying the input signal in one or more low noise amplifiers; and supplying the amplified input signal from the one or more low noise amplifiers to the first set of mixers and the second set of mixers.

[0037] Optionally, in the preceding aspect, the one or more low noise amplifiers are configured to provide the amplified input signal as a differential output provide the amplified input signal as a differential output to the first set of mixers and the second set of mixers as a positive side output of the low noise low noise amplifiers. The baseband IQ signal is further generated from the input signal by: receiving at each of a third set of mixers a corresponding one of the first set of clock signals and a negative side output of the low noise low noise amplifiers, generating in a first of the third set of mixers the inverse of the in-phase component of the differential IQ signal, generating in a second of the third set of mixers the quadrature component of the differential IQ signal, receiving at each of a fourth set of mixers a corresponding one of the second set of clock signals and the input signal, generating in a first of the fourth set of mixers the quadrature component of the differential IQ signal, and generating in a second of the fourth set of mixers the inverse of the quadrature component of the differential IQ signal.

[0038] Optionally, in the two preceding aspects, the method of receiving a signal further comprises: receiving and supplying the input signal to one or more low noise amplifiers from an antenna.

[0039] Optionally, in any of the preceding aspects of a method of receiving a signal, receiving the 6-phase clock signal includes: generating the first set of clock signals from a voltage controller oscillator, and generating the second set of clock signals from the first set of clock signals by introducing a phase shift to the first set of clock signals.

[0040] Optionally, in any of the preceding aspects of a method of receiving a signal, generating from the components of the differential IQ signal the baseband IQ signal includes: receiving the in-phase components of the differential IQ signal in an analog format and generating therefrom an in-phase component of an input IQ signal in digital format; receiving the quadrature components of the differential IQ signal in an analog format and generating therefrom a quadrature component of an input IQ signal in digital format; and receiving the input IQ signal in digital format and generating therefrom the baseband IQ signal.

[0041] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements.

[0043] FIG. 1 illustrates a wireless network for communicating data.

[0044] FIG. 2 is block diagram of a wireless communication system that can be used in a network such as in FIG. 1.

[0045] FIG. 3 is a block diagram for a first embodiment of a 6-phase digitally assisted harmonic rejection transmitter using RF interpolation for improved harmonic rejection.

[0046] FIG. 4 illustrates one embodiment for the 6-phase frequency synthesizer block of FIG. 3 as a dual 3-phase frequency synthesizer.

[0047] FIG. 5 is a timing diagram showing each clock from the frequency synthesizer block of FIG. 4 and its duty ratio.

[0048] FIG. 6 shows the results of a simulation for the performance of the power amplifier for the embodiment of FIG. 3.

[0049] FIG. 7 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG. 3.

[0050] FIG. 8 is a block diagram for a first embodiment of a 6-phase digitally assisted harmonic rejection receiver using RF interpolation for improved harmonic rejection.

[0051] FIG. 9 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG. 8.

[0052] FIG. 10 presents an alternate embodiment for a receiver using RF interpolation and an overlapping 6-phase clocks.

[0053] FIG. 11 shows the results of a simulation for the performance at the output of the power amplifier for the embodiment of FIG. 10. [0054] FIG. 12 is an alternate embodiment of a receiver using digital compensation corresponding to the transmitter embodiment of FIG. 10.

[0055] FIGs. 13 and 14 present another set of alternate embodiments for a transmitter and a receiver.

DETAILED DESCRIPTION

[0056] The present disclosure will now be described with reference to the figures, which in general relate to techniques for reducing unwanted harmonic content from transmitters and receivers. Embodiments are presented for 6-phase digitally assisted harmonic rejection transmitters and receivers using RF interpolation. The transmitters and receivers include harmonic rejection mixers that use a 6-phase clock signal while also using a differential in-phase/quadrature (l/Q) input signal for the transmitter path and output signal for the receiver path. This results in crosstalk between the in-phase and quadrature components. To obtain the desired baseband signals and remove the crosstalk, a digital correction circuit forms linear combinations of the baseband l/Q signal to generate the differential l/Q signal for the mixer. By use of a differential l/Q signal, only two DACs/ADCs are needed, saving on circuitry area and power consumption while providing strong 2 ^nd , 3 ^rd , and 4 ^th clock harmonic rejection. The clock signal can be made up of two sets of 3-phase signals, each signal having a 33% duty cycle.

[0057] It is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. Indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

[0058] FIG. 1 illustrates a wireless network for communicating data. The communication system 10 includes, for example, user equipment 11A-11C, radio access networks (RANs) 12A-12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 10.

[0059] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency- division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds), to communicate with the communication devices. In general, a reference to base station may refer any of the eNB and the 5G base stations (gNB). In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB base station.

[0060] System 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0061] The user equipment (UE) 11A-11C are configured to operate and/or communicate in the system 10. For example, the user equipment 11A-11C are configured to transmit and/or receive wireless signals or wired signals. Each user equipment 11A-11C represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device.

[0062] In the depicted embodiment, the RANs 12A-12B include one or more base stations 17A, 17B (collectively, base stations 17), respectively. Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11 B, 11 C to enable access to the core network 13, the PSTN 14, the Internet 15, and/or the other networks 16. For example, the base stations (BSs) 17 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network.

[0063] In one embodiment, the base station 17A forms part of the RAN 12A, which may include other base stations, elements, and/or devices. Similarly, the base station 17B forms part of the RAN 12B, which may include other base stations, elements, and/or devices. Each of the base stations 17 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” In some embodiments, multiple-input multiple-output (MIMO) technology may be employed having multiple transceivers for each cell.

[0064] The base stations 17 communicate with one or more of the user equipment 11A-11 C over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

[0065] It is contemplated that the system 10 may use multiple channel access functionality, including for example schemes in which the base stations 17 and user equipment 11A-11 C are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base stations 17 and user equipment 11A-11 C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized. [0066] The RANs 12A-12B are in communication with the core network 13 to provide the user equipment 11 A-11 C with voice, data, application, Voice over Internet Protocol (VoIP), or other services. As appreciated, the RANs 12A-12B and/or the core network 13 may be in direct or indirect communication with one or more other RANs (not shown). The core network 13 may also serve as a gateway access for other networks (such as PSTN 14, Internet 15, and other networks 16). In addition, some or all of the user equipment 11 A-11C may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols.

[0067] The RANs 12A-12B may also include millimeter and/or microwave access points (APs). The APs may be part of the base stations 17 or may be located remote from the base stations 17. The APs may include, but are not limited to, a connection point (a millimeter wave, or mmW, CP) or a base station 17 capable of mmW communication (e.g., a mmWbase station). The mmWAPs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.

[0068] Although FIG. 1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 10 could include any number of user equipment, base stations, networks, or other components in any suitable configuration. It is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE), laptop mounted equipment (LME) and USB dongles.

[0069] FIG. 2 is block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11 A-11C or base station 17, showing some of the elements discussed in relation to the following figures. To transmit an output signal from the circuit elements of processor 111, a transmitter (Tx) RF/analog section 101 up-converts the output signal from either a baseband or an intermediate frequency (IF) range, depending on the construction of Tx digital baseband block 107 to the radio frequency (RF) range, and also amplifies and filters an outgoing transmit signal before supplying the transmit signal to the antenna 105. The transmitter (Tx) RF/analog section 101 can also be configured to perform other processes to prepare the outgoing transmit signal. The output signal generated by Tx digital baseband block 107 is provided to the Tx RF/analog section 101 in in-phase/quadrature (l/Q) format as in- phase and quadrature signals IT _X and QT _X . Although Tx digital baseband block 107 is shown as a separate block from Tx RF/analog section 101 in FIG. 2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these.

[0070] Signals are received by the antenna 105 and supplied to a receiver (Rx) RF/analog section 102. Rx section 102 performs any needed or wanted signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, before passing the signal on to other elements on the device represented at processor 111. In the embodiment of FIG. 2, the output of the Rx RF/analog section 102 is in l/Q format and the Rx digital baseband section 117 converts this to the receive signal supplied to the processor. Although the Rx digital baseband section 117 is shown as a separate block from Rx RF/analog section 102 in FIG. 2, depending on the embodiment these elements can be variously combined as circuit elements and implemented in hardware, firmware, software, or a combination of these. Additionally, although FIG. 2 represents the Tx RF/analog section 101 and Rx section RF/analog 102 as separate elements, depending on the embodiment, the transmitter and receiver paths can share many elements or be embodied as a combined transceiver. In the following, “transceiver” may be used generally to refer a combined transmitter/receiver, separate transceiver and receiver sections, or an embodiment in which one or more components (e.g., local oscillators) are shared between the transmitter and receiver.

[0071] In a transceiver, such as a mobile telephone, it is common to have undesired clock harmonics generated from the local oscillator. On the transmitter side, these clock harmonics can be mixed back to near the frequency of the desired signal through non-linearities in and creates near channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x ^th order counter inter-modulation) and also impact other wireless terminals nearby using near-by carrier frequencies. On the receiver side, a blocker signal near the desired signal’s clock harmonics frequency can fall on top of the desired signal frequency when mixed back to the baseband frequency when down-converted and degrade the received signal. Consequently, it is desirable to reduce these unwanted clock harmonics’ impact as much as possible.

[0072] Typically, some of these unwanted harmonics can be removed through multi-phase (N-phase) mixer design, with an appropriate choice of N, where the higher the value N, the more harmonics that will be removed. For example, in a typical analog IF interpolation approach, the transmitter or receiver can use two digital to analog converters (DACs) and two analog to digital converters with two IF circuitry pairs. This approach relies on an IF resistive interpolation network between IF and RF stages for a 4-phase to N-phase conversion in a transmitter path (or N-phase to 4-phase for a receiver). This resistive interpolation network typically results in increased power consumption due to mixer switch loading and added noise. A typical digital interpolation uses N/2 DACs/ADCs and N/2 IF pairs (e.g. for a 6-phase transmitter harmonic rejection system, three DACs and IF pairs would be needed). This leads to increased IF area requirements and power consumption. Digital interpolation provides good performance, but this performance is overkill and in many cases comes at the expense of added IF area/power. The following embodiments address the increased IF area/power in digital interpolation by requiring only two DACs/ADCs/IF pairs and uses the concept of RF interpolation to alleviate the added power and noise resulting from analog IF interpolation.

[0073] The following presents embodiments for transmitters and receivers, and a Flarmonic Rejection Mixer (FIRM) mixer structure, that uses mixer switches to perform RF interpolation and then applies digital compensation to correct for any resulting in- phase/ quadrature (l/Q) cross talk. This approach can be used with equally-weighted or non-equally weighted and segmented or non-segmented variable gain amplifiers (in a transmitter path) and low noise amplifiers (in a receiver path). The following discussion is primarily presented in the context of 6-phase (or dual 3-phase) transmitter and receiver embodiments. Six-phase provides an opportunity to use 1 5x local oscillator (LO) clock generation for Ultra-High Band (UHB), as opposed to 2x LO clock generation for 4-phase system. This provides power savings when dealing with LO generation for sub-8GHz 5G UHB bands.

[0074] FIG. 3 is a block diagram for a first embodiment of a 6-phase digitally assisted harmonic rejection transmitter using RF interpolation for improved harmonic rejection. Considering FIG. 3 at a high level, an IQ source 107, which can be generated inside the Tx digital baseband block 107 of FIG. 2, provides the signal to be transmitted. The signal from IQ source 107 is in l/Q format, and, as described below, is converted into a differential l/Q in the signal source 241 , whose components provide the source signal to harmonic rejection block HRM 200. A frequency synthesizer block 230 of phase locked loop 233 with the voltage controlled oscillator VCO 231 supplying the 6-phase signal generator 235 provides clock signals to HRM 200. The output of HRM 200 is supplied to antenna 105 through a set of variable gain amplifiers VGA 221-/ and VGA 223-/, inductive coupler 251 , power amplifier PA 253, and filter 255.

[0075] FIG. 4 illustrates one embodiment for the 6-phase frequency synthesizer block of FIG. 3 as a dual 3-phase frequency synthesizer. The different embodiments presented in the following will mostly rely on the use of 6-phase 33% duty ratio overlapping clock signals shown in FIG. 5. However, it should be noted that the techniques described here also apply to other duty-ratio overlapping or non overlapping clock arrangements.

[0076] In the block of frequency synthesizer 230 for the embodiment of FIG. 4, a VCO 231 can be part of a phase locked loop PLL 233. The VCO can run at a frequency fVCO=1 5 ^* fLO, where fLO is the local oscillator or carrier frequency. The VCO output is fed to a first 3-phase clock generation block 435 to generate clkO, clk120 and clk240. The VCO output is also fed a 90 degrees phase shift block 437 and then to a second 3-phase generation block 439. Since the 3-phase generation block 439 is basically a divide by 1.5 operation, the initial 90 degrees phase shift becomes 60 degrees at the final carrier frequency, which means the clk60, clk180 and clk300 will be generated in block 439. For all six clocks (clkO, clk120, clk240, clk60, clk180 and clk300), each clock has duty ratio of 33.33% in this embodiment, so that the three clock signals from each of the generation blocks 235 and 239 are non-overlapping and together add up to 100%, but the clocks form the different blocks overlap.

[0077] FIG. 5 is a timing diagram showing each clock from frequency synthesizer block 230 and its duty ratio in one embodiment. As shown in FIG. 5, elk 0, clk120 and clk240 form a first set of non-overlapping signals of 3-phase clock signal and clk60, clk180 and clk300 forms a second set of non-overlapping signals of a 3-phase clock signal. Combing all six clocks, they are overlapping clocks.

[0078] Returning to FIG. 3, in the IQ signal path, the IQ data from IQ source 107 is a baseband l/Q signal with components It* and Qt* that is supplied to digital correction block 243 that, as described in more detail below, forms a differential l/Q signal with component pair I and Q from a linear combination of the pair It* and Qbt _>. Then digital to analog converters DAC_I 245-1 and DAC_Q 245-2 convert the digital signals (I, Q) pair to analog signals, which are then filtered through low pass filters (LPFs) LPF_I 247-1 and LPF_Q 247-2 to remove unwanted distortions and noise. Typically, the DACs and LPFs are differential circuits to be relatively immune from other noise sources inside the transceiver. This means in addition to the I (0 degree phase) and Q (90 degree phase) signals, the complementary signals lb (180 degree phase) and Qb (270 degree phase) are also created and provided to HRM 200. Together, the elements 107, 243, 245-1 , 245-2, 247-1 , and 247-2 form a differential l/Q signal source 241. Note that although a 6-phase clock signal is being used, only two DACs are used to provide the input signals.

[0079] The two p side intermediate outputs of HRM 200 each go to a corresponding one of VGA 221-1 or VGA-2 221-2. The input of each of these VGAs is the combined output from a set of three mixers each receiving one the set of clock signals with phases (0°, 120°, 240°) or with phases (60°, 180°, 300°): the input of VGA 221-1 is the combined output of mixer 201 receiving signal input I and clkO, mixer 202 having a grounded input and receiving clk120, and mixer 203 receiving input signal Qb and clk240, which are combined to produce a first p side intermediate output; and the input of VGA 221-2 is the combined output of mixer 204 receiving input signal Q and bclk60, mixer 205 having an input connected to ground and receiving clk300, and mixer 206 receiving the input signal lb and clk180 are combined to produce a second p side intermediate output. As the mixers 202 and 205 have their inputs connected to ground, they act as dummy mixers in this embodiment. As noted above each the clock signals of each set has a duty cycle of 1/3, or 33%, and are non-overlapping, but each set together add up to 100%. Taken together, the two sets of three clock signals that make up the 6-phase signal are overlapping as in the embodiment of FIG. 5.

[0080] A similar arrangement is used for the n side intermediate outputs of HRM 200, each going to one of a corresponding VGA 223-1 or VGA 223-2. The input of each of these VGAs is the combined output from a set of three mixers each receiving one the same set of clock signals, but, except for the dummy mixers, now the inverse of the corresponding input on the n side: the input of VGA 223-1 is the combined output of mixer 211 receiving lb and clkO, dummy mixer 212 receiving clk120, and mixer 213 receiving Q and clk240 to produce a first n side intermediate output; and the input of VGA 221-2 is the combined output of mixer 214 receiving Qb and clk60, dummy mixer 215 receiving clk300, and mixer 216 receiving I and clk180 to produce a second n side intermediate output. As noted above each of these clock signals has a duty cycle of 1/3, or 33%, and are non-overlapping, but each set together add up to 100%.

[0081] The RF intermediate outputs from the p side mixers are amplified by the VGAs 221-1 and 221-2 and combined to provide a p side output signal from FIRM 200, with the RF intermediate outputs from the n side mixers similarly amplified by the VGAs 223-1 and 223-2 and combined to provide an n side output signal from FIRM 200. To convert the RF output from the VGAs to a single ended output, an inductive coupler 251 can be used, with the combined p side output and the combined n -side output connected across a first coil of inductive coupler 251 and the second coil of the inductive coupler 251 having one side set at ground and the other side providing a single-ended signal at the output. A power amplifier PA 253 amplifies the single-ended output and the PA output is filtered through a RF filter 255 to remove unwanted distortions. Finally, the filtered RF output is fed to the antenna 105 to be transmitted.

[0082] Typically, the mixers inside FIRM 200 are passive mixers in cellular applications, which means overlapping clock creates cross talk among different paths. To avoid this, segmented VGAs 221 -1 , 221-2, 223-1 , and 223-2 can be use as shown in FIG. 3 such that each individual path has non-overlapping clocks.

[0083] The embodiment of FIG.3 applies transmitter RF interpolation using the overlapping 6-phase 33% duty ratio clocks discussed with respect to Figure 5. The dummy mixers 202, 205, 212, and 215 are used to ensure proper cyclical switching through all clock phases. In other words, the added clock periods for each segmented VGA (221-1 , 221-2, 223-1 , and 223-2) should add up to a full period of 100%. The use of dummy mixers allows reducing the total number of mixers to 12 (compared to embodiments to be discussed later), but may have the impact on the output transmitter noise falling in a nearby receive band. This makes this configuration more suited for time-division multiplexing (TDD) UFIB bands where receive band noise is not a concern. Although the embodiment of FIG. 3 shows equally weighted VGAs (i.e. VGAs with equal gains), the approach can also be applied to cases where the segmented VGAs are designed to have unequal gains.

[0084] Concerning the digital correction block 243, I and Q are the differential analog l/Q waveforms at the output of I and Q DACs LPF_1 247-1 and LPF_Q 247-2, respectively. Assuming unity gain passive mixers and VGAs for illustrative purposes only (and without loss of generality), it can be shown then that the RF output complex envelope (Vout) for this embodiment is given by:

Vout = I + y ₂ *Q + j ^* sqrt(3)/2 ^* Q . from above equation it is evident that part of the Q signal (highlighted in bold typeface) leaks into the (in-phase) I path. Also, note that the desired I and Q terms are not equally scaled. This l/Q cross talk can be compensated digitally inside the Tx digital front end (DFE) before the DAC inputs by the digital correction block 243.

[0085] The applied digital compensation in this case is shown in the digital correction block 243 and is the linear combination: l=lbb ^* sqrt(3)/2-Qbb/2 ; and Q — Qbb .

In the above, Iw _> and Qbb are the “ideal” transmitter digital baseband l/Q signal components that come from source 107 and that are the intended l/Q signal meant to be transmitted. With this correction factor, Vout = sqrt(3)/2 (It* + j ^* Qbb), which, normalization factor aside, is the desired output for a baseband l/Q signal of Iw _> + j ^* Qbb.

[0086] The transmitter of FIG. 3 can provide 2 ^nd , 3 ^rd , and 4 ^th clock harmonic rejection. The use of a 33% duty ratio 6-phase embodiment rejects the 2 ^nd and 4 ^th harmonics because each of the three phases (0, 60, and 120) LO clocks have their corresponding equally weighted differential pairs (180, 240, and 300) LO clocks. This ensures the 2 ^nd and 4 ^th harmonic cancellation. Additionally, as the 3 ^rd harmonic content is rejected because a 33% duly-ratio LO clock naturally has no 3 ^rd harmonic content. The simulation of FIG. 6 illustrates the performance at the PA 253 output of this RF interpolation HRM architecture. It can achieve a performance comparable to a standard 6-Phase HRM if the impairments are managed properly. In the transmitter chain of the embodiment of FIG. 3, the PA 253 is shown as a single-ended design, which means it has strong even-order of non-linearity so that there will be some 2 ^nd harmonics to CIM2 conversion introduced by the power amplifier.

[0087] FIG. 6 shows the results of a simulation for the performance at the output of the power amplifier for the embodiment of FIG. 3. More specifically, the plot of FIG. 6 plots the output of the 6-phase power amplifier output in decibels (dB), normalized so that the desired transmitter (Tx) signal is at OdB, as a function of frequency. In the plot of FIG. 6, the desired signal frequency (about 1 .2288x10 ⁸ Hz) is chosen to be lower than an actual RF target frequency for fast simulation purpose. In addition to the desired Tx signal, at a somewhat lower frequency are a peak due to LO leakage, down by about -60dB, and a peak due to image distortion, down by over -80dB.

[0088] With respect to the harmonics, for the second order counter inter-modulation FIG. 6 shows a peak on the positive side CIM2p down by -90dB. There are no other significant spikes. Consequently, the simulation results of FIG. 6 illustrate that the performance at output of power amplifier PA 253 of the 6-phase digitally assisted harmonic rejection transceiver using RF interpolation is comparable to a standard 6- Phase HRM. The spectrum of this system shows the levels of all CIM distortion are sufficiently low for cellular applications. [0089] FIG. 7 is a flowchart illustrating a first embodiment for the operation of a transceiver as in the embodiment of FIG. 3. At 701 the initial baseband l/Q signal (Iw _> , Qbb) is received from the IQ source 107. The input signal for the FIRM 200 are generated at 703 from the signal source 241 . The digital correction block 243 forms the l/Q signal pair (I, Q) supplied to FIRM 200 from a linear combination of the source baseband l/Q signal (Iw _> , Qbb). In the embodiment of FIG.3, the differential signal pairs I, lb and Q, Qb are generated from the l/Q signal from correction block 243 by DACs 245-1 , 245-2 and LPFs 247-1 , 247-2.

[0090] At 705 the frequency synthesizer 230 generates, and FIRM 200 receives, the LO clock signals. The LO clock signals include 6-phase clock signals as illustrated above with respect to FIG. 5, where in the embodiment illustrated with respect to FIG. 4 these can be the three components of the first 3-phase clock signal generator 435 and the three components of the second 3-phase clock signal generator 439. In the embodiment of FIG. 3, the first 3-phase clock signal is the clock signals ClkO, Clk120, and Clk240 from generator block 235, all with a duty ratio of 1/3, and second 3-phase clock signal is shifted by 60 degrees from the first 3-phase signal and is the clock signals Clk60, Clk180, and Clk300 from generator block 239, all with a duty ratio of 1/3. Although the flowchart of FIG. 7 presents its elements in a particular sequence, it will be understood that these can all be performed concurrently (i.e. , 701 , 703, and following elements are going at the same time during operation) to generate the output signal when the circuit of FIG. 3 is transmitting.

[0091] At 707, the clock signals of the first set of clock signals is mixed with the input I and Qb components of the input signal. For example, in the embodiment of FIG. 3, in the first set of mixers on the p-side of FIRM 200 the clock signal components (0, 240) are respectively mixed with the components (I, Qb) in mixers 201 and 203, with the clock signal component clk120 used by the dummy mixer 202. In alternate embodiments presented below, the mixer 202 can also receive a component of the l/Q signal rather than have its signal input grounded. At 709 the outputs of the mixers 201 , 202, and 203 are combined to form a first intermediate signal for the p side, which is then amplified in VGA 221-1 . [0092] Concurrently with 707 and 709, 711 and 713 are performed. At 711 , the second set of clock signals is mixed with the I and Qb components of the input signals. For example, in the embodiment of FIG. 3, in the second set of mixers on the p-side of FIRM 200 the clock signals (clk60, clk180) respectively mixed with (Q, lb) in mixers

204 and 206, where mixer 205 is a dummy mixer receiving the clk300 clock signal and with a grounded signal input. In alternate embodiments presented below, the mixer

205 can also receive a component of the differential l/Q input signal. At 713 the outputs of mixers 204, 205, and 206 are combined to form a second intermediate signal for the p side, which is then amplified in VGA 221 -2. In a two sided embodiment as in FIG. 3, the two n side intermediate outputs are generated as described above to complement the p side process of 707-713.

[0093] At 715, the first and second intermediate signals are combined to generate the output signal for, in the two sided embodiment of FIG. 3, the p side of FIRM 200. After amplification of the intermediate signals, the outputs of the VGA 221-1 and 221- 2 are combined to provide the output signal for the p side of FIRM 200. In the two sided embodiment of FIG. 3, on the n side intermediate outputs are similarly combined to provide the output signal for the n side of FIRM 200.

[0094] The output signals are then transmitted in 717. In a two sided embodiment like FIG. 3, the p side and n side outputs are converted to a single sided output at the coils of inductive coupler 251. The single sided output is then amplified in power amplifier PA 253, filtered at filter 255, and then transmitted from antenna 105.

[0095] Embodiments of a receiver configuration can be similar to the transmitter configuration of FIG. 3, but in a “reversed” fashion, i.e. variable gain amplifiers replaced by low noise amplifiers and DACs replaced by ADCs. Similar to the transmitter case, when RF interpolation is applied to a receiver, it also results in l/Q cross talk and digital compensation can be used to extract the desired baseband l/Q signal. The corresponding digital baseband compensation can be done inside a receiver digital front end and applied to the ADC l/Q outputs as shown in the embodiment of FIG. 8. [0096] FIG. 8 is a block diagram of an embodiment for a 6-phase receiver system which rejects blockers that are located at or near 2 ^nd , 3 ^rd and 4 ^th clock harmonics. The overall structure of the receiver embodiment of FIG. 8 is similar to the transmitter embodiment of FIG. 3, except, roughly speaking, with the signal paths reversed. In the receiver embodiments presented here, a segmented low noise amplifier (LNA) is used to avoid overlapping cross-talk.

[0097] More specifically, the frequency synthesizer 830 can be of the same or a similar structure to frequency synthesizer 230 of FIG. 3, where VCO 831 , PLL 833, and 6-phase generation block 835 can operate as described above with respect to the corresponding elements 231 , 233, and 235.

[0098] Rather than receiving a differential l/Q input signal, FIRM 700 now generates a differential l/Q output. FIG. 8 is again a two sided embodiment. The complimentary output signal pairs (I, lb) and (Q, Qb) act as the differential inputs to a set of low pass filters and analog to digital converters. More specifically, the (I, lb) pair are the differential input to LPF_I 847-1 , whose output then goes to ADC_I 845-1 to give the (single ended) in-phase component of the output. Similarly, the (Q, Qb) pair are the differential input to LPF_Q 847-2, whose output then goes to ADC_Q 845-2 to give the (single ended) quadrature component of the 3-phase output. The digital correction block 843 then takes linear combinations of the input l/Q signal components (I, Q) to extract the baseband l/Q signal components (Ibb, Qbb) similarly to the process described above for the inverse process in correction block 243.

[0099] The inputs to FIRM 800 are from a segmented LNA of LNA 821-1 and LNA 821-2 on the p side and LNA 823-1 and LNA 823-2 on the n side, each connected to receive a signal from the antenna 105 by way of RF filter 855. Alternate embodiments could use a pair of LNAs with differential outputs having the p side output of each going to a corresponding set of p side mixers in FIRM 800 and the n side output of each going to the corresponding set of n side mixers in FIRM 800.

[00100] Within FIRM 800, the p side output from LNA 821-1 goes to the first set of p side mixers 801 , 802, and 803 to be respectively mixed with clkO, clk120 and clk240 to generate the output component I in 801 and Qb in 803, with 802 being a dummy mixer with grounded output. On the n side the output from LNA 823-1 goes to the first set of p side set of mixers pair 811 , 812, and 813 to be respectively mixed with clkO, clk120, and clk240 to generate the output components lb, a grounded dummy output, and Q.

[00101] Similarly, the p side output from LNA 821-2 goes to the set of p side mixers 804, 805, and 806 respectively mixed with clk60, clk300 and clk180 to generate the output components Q, a grounded dummy output, and lb. On the n side, the output from LNA 823-2 goes to the set of n side set of mixers 814, 815, and 816 to be respectively mixed with clk60, clk300, and clk180 to generate the output components Qb, a grounded dummy output, and I.

[00102] FIG. 9 is a flowchart illustrating an embodiment for the operation of a receiver as in the embodiment of FIG. 8. At 901 , an input signal is received. Referring to the embodiment of FIG. 8, the input signal is received by the antenna 105 and then goes to the segmented LNAs 821-1 , 821-2, 823-1 and 823-2, with the outputs supplied to the p side and n side of HRM 800. At 903 the frequency synthesizer 830 generates, and HRM 800 receives, the LO clock signals. The LO clock signals in the embodiments of FIG. 8 can include the 6-phase clock signals of the two sets clkO, clk120, and clk240 and clk60, clk180, and clk300, all of which have a duty cycle ratio of 1/3 (33%).

[00103] At 905, for each component of the first set of clock signals (clkO, clk120, and clk240), the p side input signal from the LNA 821-1 is mixed with the clock signals to generate to an I output from mixer 801 and Qb output from mixer 803. As on the transmitter embodiment of FIG. 3, the mixer 802 receiving clk120 is a dummy mixer and has its output grounded. At 907, for each component of the second set of clock signals (clk60, clk180, and clk300), the p side input signal from the LNA 821-2 is mixed with the clock signals to generate to a Q output from mixer 804 and lb output from mixer 806. As on the transmitter embodiment of FIG. 3, the mixer 805 receiving clk300 is a dummy mixer and has its output grounded.

[00104] Together, the output from 905 and the output from 907 provide components of an l/Q output. The differential can then go the LPFs 747-1 and 747-2, and 747-3, followed ADCs 745-1 and 745-2 to generate the (one sided) digital l/Q signal with components (I, Q). To remove the in-phase/quadrature cross talk and generate the desired baseband l/Q signal, at 909 the digital correction block 843 forms linear combinations of the l/Q from HRM 800 to provide the baseband l/Q signal of components It* and Qbt>.

[00105] For a two sided embodiment as in FIG. 8, the n side outputs of the LNAs 823-1 and 823-2 respectively go to the first set of n side mixers (811 , 812, 813) to be mixed with the first set of clock signal and to the second set of n side mixers (814, 815, 816) to be mixed with the second set of clock signals. These respectively generate another copy of the l/Q output signal that can similarly be used in generating the IQ output.

[00106] Relative to previous approaches that require more IF circuit area or a power hungry and noisier analog IF interpolation network, the embodiments described with respect to FIGs. 3-9 can reduce IF area and remove the need for IF interpolation. This particular embodiments of FIG. 3 and FIG. 8 also allow for a relatively small number of mixers, although this can be at the expense of some compromise to transmitter noise falling in the receive band, although in applications such as time-division multiplexing (TDD) UFIB bands where receive band noise is less of a concern.

[00107] FIG. 10 presents an alternate embodiment for a transmitter using RF interpolation and overlapping 6-phase 33% duty ratio clocks. As with the embodiment described with respect to FIG. 3, this arrangement provides good 2 ^nd , 3 ^rd , and 4 ^th harmonic rejection. The transmitter embodiment of FIG. 10 uses 24 mixers with equally weighted VGAs and no dummy mixers, providing improved noise performance and can be suitable for low band and high band applications as there are not receiver band noise concerns.

[00108] FIG. 10 does not show a differential l/Q in the signal source, frequency synthesizer block, power amplifier, filter, or antenna, but these can be implemented as differential l/Q in the signal source 241 , frequency synthesizer block 230, PA 253, filter 255, and antenna 105 of FIG. 3. FIRM 1000 again receives the (corrected) differential l/Q input signal components I, lb and Q, Qb along with the 6-phase clock signals including a first set of clkO, clk120, clk240 and a second set of clk60, clk180, clk300.

[00109] On the p side, HRM1000 includes a first set of mixers 1001 ,1002, 1003 and a second set of mixers 1004, 1005, 1006 that are connected similarly to the six p side mixers of the embodiment of FIG. 3, except instead of the two dummy mixers whose inputs are grounded, mixer 1002 now mixes clk120 with Q and mixer 1006 now mixes clk300 with Qb. The outputs of 1001 , 1002, and 1003 are combined to form a first p side intermediate output that is then amplified in VGA 1021-1 and supplied to the p side of the first coil of inductive coupler 1051. Similarly, the outputs of 1004, 1005, and 1006 are combined to form a second p side intermediate output that is then amplified in VGA 1021-2 and supplied to the p side of the first coil of inductive coupler 1051.

[00110] The p side of HRM now also include an additional two sets of three mixers relative to the embodiment of FIG. 3. The set 1007, 1008, 1009 receive the same clock signals as the set 1001 , 1002, 1003, but mixes them with different components of the differential l/Q input, with 1007 mixing clkO with Q, 1008 mixing clk120 with lb, and 1009 mixing clk240 with lb. The outputs of 1007, 1008, and 1009 are then combined to form a third p side intermediate output that is amplified in VGA 1021-3 and supplied to the p side of the first coil of inductive coupler 1051 .

[00111] The fourth set of p side mixers 1010, 1011 , 1012 receive the same clock signals as the set 1004, 1005, 1006, but mix them with different components of the differential l/Q input, with 1010 mixing clk60 with I, 1011 mixing clk180 with Qb, and 1012 mixing clk300 with I. The outputs of 1010, 1011 , and 1012 are then combined to form a fourth p side intermediate output that is amplified in VGA 1021-4 and supplied to the p side of the first coil of inductive coupler 1051 .

[00112] The n side of FIRM 1000 mirrors the p side, with the mixers 1051-1062 respectively receiving the same clock signals as mixers 1001-1012, but with each of inputs of the l/Q signal being replaced by inverse so that, relative to the corresponding p side mixer (l->lb, Q->Qb, lb->l, and Qb->Q). The outputs of the four sets of n side mixers are then combined to form four intermediate n side outputs that are then amplified in the VGAs 1023-1 , 1023-2, 1023-3, and 1023-4, which are in turn combined and supplied to the n of the first coil of inductive coupler 1051.

[00113] For the transmitter of the embodiment of FIG. 10, the complex RF output envelope is given by:

Vout = 2 ^* l + Q + j ^* sqrt(3) ^* Q , where the resulting cross talk term is again highlighted in bold typeface. Also, note that the desired I and Q terms are not equally scaled. Although increased by an overall factor of 2, this is otherwise the same combination of terms as for the transmitter of embodiment of FIG. 3. Consequently, the applied digital compensation for the correction block can again be shown to be: l=lbb ^* sqrt(3)/2-Qbb/2 ; and Q — Qbb .

In the above, Iw _> and Qbb are again the “ideal” transmitter baseband l/Q signal components that come source 107 that are the intended l/Q signal meant to be transmitted.

[00114] FIG. 11 shows the results of a simulation for the performance at the output of the power amplifier for the embodiment of FIG. 10 and is presented similarly to FIG. 6. More specifically, the plot of FIG. 11 plots the output of the 6-phase power amplifier output from the embodiment of FIG. 10 in decibels (dB), normalized so that the desired transmitter (Tx) signal is at OdB, as a function of frequency. In the plot of FIG. 6, the desired signal frequency (about 1.2288x10 ⁸ Flz) is chosen to be lower than an actual RF target frequency for fast simulation purpose. In addition to the desired Tx signal, at a somewhat lower frequency are a peak due to LO leakage, down by about -60dB, and a peak due to image distortion, down by over -80dB.

[00115] With respect to the harmonics, for the second order counter inter-modulation FIG. 6 shows a peak on the positive side CIM2p down by around -90dB. Of the other significant spikes, the largest is CIM5, that is down by -80dB. Consequently, the simulation results of FIG. 11 illustrate that the performance at output of power amplifier PA 1053 of the 6-phase digitally assisted harmonic rejection transceiver using RF interpolation is comparable to a standard 6-Phase FIRM. The spectrum of this system shows the levels of all CIM distortion are sufficiently low for cellular applications. [00116] FIG. 12 is an alternate embodiment of a receiver using digital compensation corresponding to the transmitter embodiment of FIG. 8. FIG. 12 does not include a frequency synthesizer or the elements for converting the differential l/Q signal to the baseband (one sided) components lbt _> , Qbt _> , but these can be as described above for the frequency synthesizer 830 and LPFs 847-1 , 847-2, ADCs 845-1 , 845-2, and digital correction block 843 of FIG. 8. FIG. 12 does, as in FIG. 8, include an antenna 105 connected to a filter 1255, which in turn supplies the signal from the antenna 105 to a set of low noise amplifiers.

[00117] FIRM 1200 includes 12 mixers on each of the p side and n side arranged as for FIRM 1000 for the receiver of FIG. 10, but where the input is now from one of the LNAs and the output of each mixer is one of the components of the differential l/Q signal. More specifically, on the n side LNA 1221-1 supplies mixers 1201 , 1202, 1203 with the clock signals clkO, clk120, clk240 to respectively generate I, Q, Qb; LNA 1221 - 2 supplies mixers 1204, 1205, 1206 with the clock signals clk60, clk180, clk300 to respectively generate Q, lb, Qb; LNA 1221-3 supplies mixers 1207, 1208, 1209 with the clock signals clkO, clk120, clk240 to respectively generate Q, lb, lb; and LNA 1221- 4 supplies mixers 1210, 1211 , 1212 with the clock signals clk60, clk180, clk300 to respectively generate I, Qb, I.

[00118] The n side FIRM 1200 mirrors the p side, but with the components of the differential l/Q signal replaced by their inverses. More specifically, LNA 1223-1 supplies mixers 1251 , 1252, 1253 with the clock signals clkO, clk120, clk240 to respectively generate lb, Qb, Q; LNA 1223-2 supplies mixers 1254, 1255, 1256 with the clock signals clk60, clk180, clk300 to respectively generate Qb, I, Q; LNA 1223-3 supplies mixers 1257, 1258, 1259 with the clock signals clkO, clk120, clk240 to respectively generate Qb, I, I; and LNA 1223-4 supplies mixers 1260, 1261 , 1262 with the clock signals clk60, clk180, clk300 to respectively generate lb, Q, lb.

[00119] Compared to the embodiment of FIG. 3 and 8, the embodiment of FIG. 10 can exhibit improved transmitter noise in the receive band and can be more suited for frequency division multiplexing in low band and high band cellular applications. This improvement in noise reduction comes at the expense of added numbers of mixer switches, although in many implementations this is not a significant area increase. [00120] FIGs. 13 and 14 present another set of alternate embodiments for a transmitter and a receiver. Structurally, FIGs. 13 and 14 are similar to FIGs. 10 and 12, but with a different assignment of the l/Q components to the mixers. The p side of FIRM 1300 includes the four sets of three mixers (1301 , 1302, 1303), (1304,1305, 1306), (1307, 1308, 1309), and (1310, 1311 , 1312) that receive the same sets of clock signals as the corresponding mixers in the embodiment of FIG. 10, but now receive the inputs (I, Q, Qb), (Q, lb, Qb), (I, Q, lb), and (I, lb, Qb). Relative to FIG. 10, the non dummy mixer from FIG. 3 receive the same inputs, but the inputs supplied to the other mixers are rearranged. Consequently, FIRM 1300 will operate similarly to FIRM 1000, but will use a different linear combination of the baseband l/Q signal to generate the differential l/Q signal. As in FIG. 10, the four sets of three mixers have their outputs combined to form four p side intermediate output signals that are the amplified in the VGAs 1321 -1 , 1321 -2, 1321-2, and 1321-3, combined, and then supplied to the p side of the first coil of the inductive coupler 1351.

[00121] On the n side of FIRM 1300, the four sets of three mixers (1351 , 1352, 1353), (1354,1355, 1356), (1357, 1358, 1359), and (1360, 1361 , 1362) receive the same sets of clock signals as the corresponding mixers in the embodiment of FIG. 10, but now receive the inputs (lb, Qb, Q), (Qb, I, Q), (lb, Qb, I), and (lb, I, Q). Relative to FIG. 10, the non-dummy mixer from FIG. 3 receive the same inputs, but the inputs supplied to the other mixers are again rearranged. Consequently, FIRM 1300 will operate similarly to FIRM 1000, but will use a different linear combination of the baseband l/Q signal to generate the differential l/Q signal. As in FIG. 10, the four sets of three mixers have their outputs combined to form four n side intermediate output signals that are the amplified in the VGAs 1323-1 , 1323-2, 1323-2, and 1323-3, combined, and then supplied to the n side of the first coil of the inductive coupler 1351 .

[00122] The configuration of FIG. 13 has a higher output power than and a lower digital image compensation. As discussed in more detail below, the complex output envelop for the embodiment of FIG. 13 is given by:

Vout = 2.5Ί - 1/2*Q+ j*sqrt(3)/2*l + j ^* 3 ^* sqrt(3)/2 ^* Q , where the resulting cross talk terms are again highlighted in bold typeface. The corresponding correction factor is discussed and determined below, where the above expression corresponds to Eq. 5 below. Relative to FIG. 10, the embodiment of FIG. 13 can provide higher output and lower digital image correction.

[00123] The receiver of FIG.14 is arranged similarly to the receiver of FIG. 12, but with the outputs assigned differently. More specifically, antenna 105 is connected to filter 1455 to supply an received signal to LNAs 1421-1 , 1421-2, 1421-3, and 1421-4 on the p side and LNAs 1423-1 , 1423-2, 1423-3, and 1423-4 on the n side. The sets of mixers (1401 , 1402, 1403), (1404, 1405, 1406), (1407, 1408, 1409), (1410, 1411 , 1412) are arranged as the corresponding mixers on the p side of FIG. 12, but now the outputs are assigned respectively as (I, Q, Qb), (Q, lb, Qb), (I, Q, lb), and (I, lb, Qb). On the n side, the sets of mixers (1451 , 1452, 1453), (1454, 1455, 1456), (1457, 1458, 1459), (1460, 1461 , 1462) are arranged as the corresponding mixers on the n side of FIG. 12, but with the outputs now assigned respectively as (lb, Qb, Q), (Qb, I, Q), (lb, Qb, I), and (lb, I, Q).

[00124] With respect to determining the correction factor for the linear combination of the baseband l/Q signal used to generate the differential l/Q signal for the harmonic rejection mixer in the embodiment of FIGs. 14 and 15, let l(t) be the baseband in-phase time domain signal and Q(t) be the baseband quadrature time domain signal. Ignoring the time argument for notational simplicity, this gives the complex envelope:

XL = I + jQ , and the corresponding image (XL ^* ) is simply the conjugate:

XL ^* = I - jQ .

To have no cross-talk between the in-phase and quadrature components, the desired complex envelope RF output signal after RF interpolation should take the form:

Vout_desired = A ^* XL(t) = A ^* [l(t) + jQ(t)] , (Eq. 1 ) where A is a complex scaling factor that does not impact the quality of the transmitted (or received) signal.

[00125] A 6-phase RF interpolation, however, normally results in l/Q cross talk which produces an undesired image signal component (XL ^* ). Thus, the resulting RF output signal after 6-phase RF interpolation can be expressed as

Vout = A ^* XL + B ^* XL ^* , (Eq. 2) where the second term on the right side of Eq. 2 represents the undesired image signal that needs to be corrected (or cancelled) digitally. Classically, the correction to the second term image in Eq. 2 is done by injecting a digital image cancellation term scaled by -B/A. In other words, the digital correction (input to the l/Q Tx DACs) in general can be expressed as:

I + jQ = XLbb -B/A ^* (XL ^* bb) = Ibb + j ^* Qbb - B/A ^* (l _b -jQbb) , (Eq. 3) where Ibb and Qbb are the original digital in-phase and quadrature baseband signals, respectively. Thus, to determine the correction for any 6-phase RF interpolation embodiment, we simply need to determine the terms A & B in Eq. 2 above that result from the RF interpolation action.

[00126] In the embodiment of FIGs. 13 and 14, when considering the transmitter of FIG. 13 (where a similar argument can be made for the receiver of FIG. 14), and considering only the single ended positive connections of the transmitter low pass filter output I and Q outputs (corresponding to the outputs of LPF_I 247-1 and LPF-Q 247- 2), the Ί” baseband filter output is connected to the 0 deg phase LO clock (clkO, or P0) twice (mixers 1301 , 1307) and to the 60deg phase LO clock (cllk60, or P60) once (mixer 1310). Similarly, the Q baseband filter output is connected to the 60deg phase LO clock once (mixer 1304) and to the 120deg phase LO clock twice (mixers 1302, 1308). Thus, after transmitter up-conversion and combining with the equally weighted transmitter VGAs, the complex envelop RF output signal can be expressed as:

Vout = l ^* (2 ^* P0 + P60) + Q ^* (P60 + 2 ^* P20) , (Eq. 4) where:

P0 = exp(j ^* 0) = 1 ;

P60 = exp(j ^* PI/3) = 0.5 + j ^* sqrt(3)/2 ; and P120 = exp(j ^* 2 ^* PI/3) = -0.5 + j ^* sqrt(3)/2 .

Substituting P0, P60, and P120 into Eq. 4 above gives:

Vout = 2.5Ί - y ₂ *Q+ j*sqrt(3)/2*l + j ^* 3 ^* sqrt(3)/2 ^* Q . (Eq. 5)

Where the bold typeface terms show the resulting l/Q cross talk terms. Also, note that the desired I and Q terms are not equally scaled.

[00127] Noting that: (Eq. 6.1 ) Q = -j ^* ½ ^* ( XL - XL ^* ) . (Eq. 6.2)

Substituting Eq 6.1 and Eq 6.2 into Eq. 5, and rearranging terms, it can be shown that for the embodiment of FIG. 13 that:

Vout = (2.5490 + j0.6830) ^* XL + (-0.0490 + jO.1830) ^* XL ^* . (Eq. 7) Note now that Eq. 7 has the form of Eq.2 above, where:

A = (2.5490 + j0.6830) ; and B = (-0.0490 + j0.1830) .

Substituting the A and B values into Eq. 3 above, the digital correction for the embodiment of FIG. 13 takes the form:

I — Ibb — 0.07081 ^* Qbb ; and Q — Qbb — 0.07081 ^* lbb .

[00128] For all of the embodiments presented here, the use of a 33% duty ratio 6- phase embodiment rejects the 2 ^nd and 4 ^th harmonics because each of the three phases (0, 60, and 120) LO clocks have their corresponding equally weighted differential pairs (180, 240, and 300) LO clocks. This ensures the 2 ^nd and 4 ^th harmonic cancellation. Additionally, as the 3 ^rd harmonic content is rejected because a 33% duly- ratio LO clock naturally has no 3 ^rd harmonic content.

[00129] The technology described herein can be implemented using hardware, firmware, software, or a combination of these. The software or firmware used can be stored on one or more processor readable storage devices to program one or more of the blocks of FIGs. 3-14 to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information, and which can be accessed by the components described above. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

[00130] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[00131] In alternative embodiments, some or all of the software or firmware can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/ storage devices, peripherals and/or communication interfaces.

[00132] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be clear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

[00133] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[00134] The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

[00135] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.

[00136] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.