CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of (i) U.S. Provisional Application No. 62/711,432, filed July 27, 2018, entitled“Adaptive Voltage Scaling of Receiver”, naming Armin Tajalli, of (ii) U.S. Provisional Application No. 62/683,442, filed June 11, 2018, entitled“Adaptive Voltage Scaling of Receiver”, naming Armin Tajalli, of (iii) U.S. Provisional Application No. 62/597,902, filed December 12, 2017, entitled“Adaptive Voltage Scaling of Receiver with Decision Feedback Equalization”, naming Armin Tajalli, and of (iv) U.S. Provisional Application No. 62/597,415, filed December 12, 2017, entitled“Adaptive Voltage Scaling of Receiver with Decision Feedback Equalization”, naming Armin Tajalli, all of which are hereby incorporated herein by reference in their entirety for all purposes.

REFERENCES

[0002] The following prior applications are herein incorporated by reference in their entirety for all purposes:

[0003] U.S. Patent Application No. 15/835,648, filed December 8, 2017, naming Armin Tajalli, entitled “Methods and Systems for Providing Multi-Stage Distributed Decision Feedback Equalization”, hereinafter identified as [Tajalli I]

[0004] This application also makes reference to the following applications for purposes of historical information or descriptive clarification:

[0005] U.S Patent No. 9,288,089, filed May 20, 2010 as Application 12/784,414 and issued March 15, 2016, naming Harm Cronie and Amin Shokrollahi, entitled“Orthogonal Differential Vector Signaling”, hereinafter identified as [Cronie]

[0006] U.S. Patent Application No. 13/842,740, filed March 15, 2013, naming Brian Holden, Amin Shokrollahi, and Anant Singh, entitled“Methods and Systems for Skew Tolerance in and Advanced Detectors for Vector Signaling Codes for Chip-to-Chip Communication”, hereinafter identified as [Holden] BACKGROUND

[0007] In many system environments, the power consumption of high speed data communications interface devices can be a significant portion of the overall power budget. A portion of this power consumption is fixed by the physical attributes of the communication network, requiring particular voltages to be induced in a predetermined transmission line impedance, that transmitted signal overcoming a known attenuation factor before being detected at a receiver. The remaining interface power consumption may be addressed by means known to the art, including integrated circuit process selection, clock speed minimization, and control of system power voltages.

[0008] For a given integrated circuit design and process, normal production variations will result in devices capable of operation over a range of clock speeds and supply voltages. Typically, unit testing will eliminate devices in which the worst case“comer” of clock speed and voltage is insufficient for correct system operation. However, that implies that significant numbers of devices are capable of operating at lower speeds and/or lower supply voltage while still satisfying the overall system performance requirements.

BRIEF DESCRIPTION

[0009] Particular circuit critical paths identified during integrated circuit design and simulation constrain the minimum required clock speed and/or supply voltage needed to satisfy system requirements. Physical instantiations of these critical paths may be extracted, and replicated within an on-chip test structure allowing their operation to be verified during normal system operation. A dynamic power control system may dynamically adjust clock speeds and/or supply voltages to minimize power consumption within these measured operational constraints.

BRIEF DESCRIPTION OF FIGURES

[0010] FIG. 1 is an embodiment of one channel of a data receiver utilizing Decision Feedback Equalization and multiple parallel processing stages.

[0011] FIG. 2 shows a critical processing path in the embodiment of FIG. 1.

[0012] FIG. 3 shows a testable instance of a critical path embodiment within one embodiment of a dynamic power control system. [0013] FIG. 4 shows a dynamic power control system as in FIG. 3 controlling system power.

[0014] FIG. 5 illustrates the tolerances and margins to be applied to the base measurement.

[0015] FIG. 6 shows additional examples of subsystems having critical subsystems measured and power controlled.

[0016] FIGs. 7-11 are block diagrams of various test environments in a data receiver, in accordance with some embodiments.

[0017] FIG. 12 is a block diagram of an apparatus for adjusting a supply voltage, in accordance with some embodiments.

[0018] FIG. 13 is a flowchart of a method, in accordance with some embodiments.

[0019] FIG. 14 is a block diagram of a hierarchical dynamic voltage scaling system, in accordance with some embodiments.

[0020] FIG. 15 is a block diagram of a digital circuit block incorporating dynamic voltage scaling, in accordance with some embodiments.

[0021] FIG. 16 is a block diagram of an analog circuit block incorporating a bandgap reference voltage generator to control a local regulator, in accordance with some embodiments.

[0022] FIG. 17 is a block diagram of an analog circuit block incorporating dynamic voltage scaling, in accordance with some embodiments.

[0023] FIG. 18 is a graph illustrating voltage-scaled trend lines of a digital monitoring circuit used in the digital circuit block, in accordance with some embodiments.

[0024] FIG. 19 is a graph illustrating voltage-scaled trend lines of a PMOS-only sheer and a Mux/Demux analog circuit used in an analog circuit block, in accordance with some embodiments.

[0025] FIG. 20 is a graph illustrating a voltage-scaled trend line of a PMOS+NMOS sheer, in accordance with some embodiments.

[0026] FIG. 21 is a block diagram of transmitting and receiving instances, each utilizing four distinct power sources. [0027] FIG. 22 is a system block diagram showing four subsystems having distinct power utilization profiles and operational characteristics.

[0028] FIG. 23 is a system block diagram showing three subsystems having distinct power utilization profiles and operational characteristics.

[0029] FIG. 24 is a flowchart of a method 2400, in accordance with some embodiments.

DETAILED DESCRIPTION

[0030] In recent years, the signaling rate of high speed communications systems have reached gigabit per second speeds, with individual transmission unit intervals measured in picoseconds. To meet such stringent timing requirements, it is necessary to minimize circuit delays by minimizing node capacitances and eliminating unnecessary processing elements. Even secondary circuit characteristics such as the settling time of an analog comparator can represent a significant proportion of the available time budget.

[0031] As one example, a conventional data communications receiver’s Decision Feedback Equalization (DFE) system stores historic values for one or more detected data values from previous receive unit intervals, and computes a DFE compensation value from these historic values that is subsequently applied to the received signal to facilitate the current unit interval’s detection. For purposes of explanation, this computation may be simply described as comprising multiplication of each previous unit interval’s data value by a predetermined scaling factor, and then summing each of these scaled results (each representing the latent effects of successive previous unit intervals on the presently received signal) to produce a composite DFE compensation value representing the cumulative predicted effect of all such previous unit intervals. In a typical receiver design, this DFE compensation value will be combined with the current receive signal input, to produce a corrected signal more accurately representing the received data value which may then be sampled in both time and amplitude to obtain a detected receive data value.

[0032] Those familiar with the art will recognize that the DFE compensation value produced as described above cannot be fully determined until the previous unit interval’s data value has been detected. Thus, as data rates increase, a point will be reached at which the information needed to produce the first term of the DFE compensation value (i.e. the received data value for the previous unit interval) is not available in time to be applied to the next unit interval’s detection. Indeed, at the highest data rates currently used in practice, this situation may exist for multiple previous unit intervals, as the detection time required for a single data value may represent multiple unit interval durations. Thus, it is common for embodiments to forgo this “closed loop” DFE method for one or more of the most recent unit intervals, instead relying on an “unrolled loop” or “speculative” generation of one or more elements of the DFE compensation value for these most recent unit intervals.

[0033] FIG. 1 illustrates one embodiment of a data receiver incorporating speculative DFE for one previous receive unit interval. This example includes a receiver front end (110 and 120,) along with a full data path for one received data bit (130, 140, 150, 160); a full receiver embodiment would typically share the single frontend with data paths for additional data bits. DFE computation 170 and Clock Data Recovery 180 subsystems may in some embodiments be shared across multiple data paths, or dedicated to a particular data path.

[0034] In the illustrated example offered without implying limitation, four received wire signals are obtained from the communications channel, possibly representing two differential signal pairs or alternatively, one four-wire stream communicating three data bits encoded using an Orthogonal Differential Vector Signaling code (ODVS), as described in [Cronie] Continuous Time Linear Equalizers 110 provide frequency-dependent amplification of the received wire signals, and Multi-Input Comparators (MIC) 120 optionally combine the amplified wire signals to reverse ODVS encoding and obtain detected data signals, as in [Holden] In differential receiving embodiments, each such MIC will have two active inputs and will functionally act as a differential line receiver, and in single-ended receiver embodiments, receive operations are performed directly on individual wire signals, bypassing the need for any MIC functionality.

[0035] One such embodiment operates with a communication unit interval of approximately 35 picoseconds, corresponding to a data rate of approximately 28 Gigabaud. To support such data rates, the example receiver incorporates two parallel processing stages 130 and 140 in each received signal data path, each of which detects the data received from one differential wire pair or ODVS subchannel during alternating unit intervals. At the described data rate, this interleaving of parallel processors allows each processing stage two unit intervals or 70 picoseconds to capture and detect each received data bit. Given that one stage of speculative DFE is used, proper operation requires that a received data bit be fully detected and available to another processing phase before the end of that subsequent processing phase’s cycle, making this a critical path for receiver operation. Additional details of this example embodiment may be found in [Tajalli I]

[0036] FIG. 2 illustrates elements of this critical path, comprising one receive processing chain from data input to detector output, and the subsequent usage of that detected data value to select a speculatively-detected result in the subsequent processing phase.

[0037] FIG. 3 shows one embodiment of a testing configuration in which such a critical path subsystem may be tested. A synthetic input data stream is created 310 and presented to the critical path subsystem 320 under test. Output from the test subsystem is validated 330 to identify whether the critical path is functioning correctly, or is out of specification. This result 335 is used to inform the Dynamic Power Controller 340 whether power 345 (or in a further embodiment, other variables such as subsystem clock) to the subsystem under test may be adjusted to a lower power consumption but potentially lower performance value. In a practical embodiment, the Critical Path Subsystem under test would comprise the subset of processing elements as identified in FIG. 2, sufficient to emulate actual operational system characteristics.

[0038] FIG. 4 shows one embodiment, in which a test environment 410 such as previously described for FIG. 3 is dynamically exercised, allowing Dynamic Power Controller 420 to be adjusted to a lower power consumption value for both the test environment 410 and the Operational Environment 430, for which 410 is a testable proxy.

[0039] In practice, systems may include one or more subsystems capable of dynamic power control, each potentially having a unique critical path and a different response characteristic of critical operational parameters such as propagation speed and signal switching threshold as subsystem power is adjusted. In some embodiments, these different response characteristics may also be dependent on operating temperature and integrated circuit process fabrication characteristics. Thus, there may be multiple test environments, test conditions, output validations, etc. that may collectively inform a single adjustment, or may individually inform different adjustments. As one example, FIG. 5 addresses a system including three distinct power control domains, which might represent an analog subsystem, a non-speed-critical digital subsystem, and a speed-critical digital subsystem. As shown at 510, the external regulator REG observes the behavior of a test circuit operating at a voltage VDDJ, under particular process and temperature conditions. However, the proper internal voltage to support that operation must include a safety factor to compensate for device aging, internal I ² R voltage drop between the internal metallization power distribution and the critical circuitry, and a safety margin to allow for noise, component and measurement tolerances, etc. Similarly, additional safety factors or margins must be applied to address additional factors between the internal power distribution of the integrated circuit and the external power system providing the regulated voltage. As shown in 510, they may include power supply noise, Package I ² R losses, High Level circuit metallization I ² R losses, and an additional safety margin.

[0040] FIG. 6 shows additional examples of power control domains and exemplar testable critical path subsystems. 610 shows power supply voltage VDDH (VDD High) being regulated externally to 0.9 volts, providing power to an output driver required to meet certain output criteria. 620 similarly shows power supply voltage VDDA (VDD Analog) being regulated in response to direct measurement of transistor threshold voltage. 630 shows VDDD (VDD Digital) being regulated to guarantee reliable operation of a high speed digital circuit, illustrated as a ring oscillator without implying limitation. In each illustrated example, the safety and measurement tolerance control margins described in FIG. 5 are applied within the measurement and control loops shown. Similarly, FIG. 21 shows a system utilizing separate VDD Analog, VDD Digital, VDD High, and VDD Support power sources.

[0041] FIG. 7 is a block diagram of an exemplary test circuit in a receiver embodiment drawn from [Tajalli I] incorporating clocked integrators 710 and 720 and multi input summation latches 730 and 740 into each speculative data sampling path for K1+ and K1-. As with the embodiment of FIG. 2, power may be reduced by decreasing supply voltage provided to the integrators and the multi input summation latches, with a resultant increase in timing delay between a clock edge initiating sampling, and output of a valid data result through, as one example path, 710, 730, 735, 750.

[0042] FIG. 8 is a block diagram of an alternative test environment, in which such a timing constrain is measured directly, rather than indirectly confirming the result of such correct timing (i.e. valid data results) were obtained. A test clock source 805 is applied to Critical Path Subsystem under test 820 along with a test data source 810. Delay measurement 830 receives the output of 820 and measures its processing delay relative to the initiating test clock. If the delay is within acceptable bounds, Dynamic Power Controller 840 may be instructed 835 to decrease supply voltage; if the delay is unacceptable, voltage may be similarly increased. [0043] In some embodiments, Delay Measurement 830 may include a Delay Locked Loop, Time-to-Voltage converter such as a ramp and sample circuit, or go/no-go comparison against a fixed or previously configured time delay reference.

[0044] FIG. 9 illustrates a test environment based on a receiver drawn from [Tajalli I] The data sampling element 910 includes a clocked integrator and multi input summation latch. As with the embodiment of FIG. 2, power may be reduced by decreasing supply voltage, with a resultant increase in timing delay between sampling clock edge and result output Q. In FIG. 9 this timing delay is measured by Delay Locked Loop 920, which is illustrated as controlling supply voltage Vdd to 910.

[0045] FIG. 10 shows another alternative data receiver embodiment. A configurable or adjustable capacitive load 1040 is shown between clocked integrator 1010 and Set/Reset Latch 1020. DLL 1030 compares the timing of output result Q with the sampling Clock, with its measurement result modifying 1040.

[0046] As described with respect to the previous figure, DLL 1030 measures the clock-to-Q processing delay, in this example through elements 1010 and 1020, including the loading effect of 1040. As detected by 1030, measured delays less than the desired amount result in an increased value for 1040, and measured delays greater than the desired amount result in a decreased value for 1040. These measurements and component adjustments may be performed independent of, or in combination with the previously described supply voltage adjustments.

[0047] FIG. 11 is a block diagram of a test environment, in accordance with some embodiments. As shown, FIG. 11 may include a replicated sampling element 1105 similar to the data sampling element depicted in [Tajalli I] In some embodiments, a periodic test signal may be applied to the input of the replica sampling element 1105. The periodic test signal may be produced from the sampling clock CK, or other periodic control rate signal generator, via a suitably configured signal attenuator. In such an embodiment, the periodic test signal may be generated by attenuating 1107 the sampling clock and applying the periodic test signal to the replica sampling element 1105. The exact amount of attenuation may depend on a desired sensitivity. In one non-limiting example, if the periodic test signal is tested to detect at lmV, then the sampling clock may be attenuated by a factor of 1000 to generate the periodic test signal to apply to the replica sheer. [0048] The replica sampling element 1105 may sample the periodic test signal to produce a periodic output Q, having some amount of introduced signal delay value. A phase detector may be configured to measure the delay between the sampling clock and the output Q of replica sampling element 1105. As shown, a delay element is included in FIG. 11 to produce a delayed version of sampling clock CK Delay. Such embodiments may ensure that the periodic test signal is sampled after a transition, rather than right on an edge of the transition. In some embodiments, an XOR phase detector 1110 is used, and the output of the phase detector may be proportional to XOR(CK, Q). In one non-limiting example, the clock period is 80 ps, and the clock-to-Q delay at 1 mV is designed to be no more than 60 ps. In such a scenario, the clock-to-Q output of the XOR phase detector will be 20 ps HIGH, and 60 ps LOW under the lock condition (shown in FIG. 11 as two lOps segments and two 30ps segments), e.g., a 25% duty cycle. In FIG. 11 , the duty cycle may be set by a programmable sensitivity voltage Vsense, e.g. 0.25V in FIG. 11. It should be noted that Vsense may be predetermined according to desired sensitivity, taking into account factors such as process variation, and dynamically updated due to temperature variation and aging. In some embodiments, V _sense may be 0.5V. If such a condition is not met, then the switching regulator generating VDDA may be incrementally increased or reduced until the desired clock-to-Q delay value is reached. In FIG. 11, the output of the phase detector 1110 may be filtered via a loop filter and sliced against a reference voltage to provide increment up/increment down signals to a digital counter 1115. The test circuit may analyze the duty cycle of the clock-to-Q measurement to determine if the supply voltage VDDA provided to the sampling element 1105 needs to be increased or decreased. The digital counter 1115 maintains an average of the up/down increment signals and controls a digital -to- analog converter 1120 to adjust the supply voltage VDDA via the DC/DC regulator 1125.

Hierarchical Dynamic Voltage Scaling System

[0049] FIG. 14 is a block diagram of a hierarchical dynamic voltage scaling system, in accordance with some embodiments. As shown, the hierarchical dynamic voltage scaling system includes a digital circuit block 1402 and two analog blocks 1404 and 1406. Each of the digital and analog circuit blocks are connected to respective switching voltage regulators located on a printed circuit board (PCB) and may include mission-mode circuits that are grouped according to various factors. In at least one embodiment, each circuit block includes mission-mode circuits grouped at least in part according to voltage supply requirements over a plurality of test comers. Such supply requirements may be quantized as voltage-scaled trendlines for each mission-mode circuit in the group of mission-mode circuits. The voltage- scaled trendlines may correspond to an analysis of each circuit over various process/variation comers that determine how much a supply voltage can be scaled down to save power, while maintaining sufficient circuit sensitivity. In other embodiments, these trendlines may correspond to such analysis specific to the particular process characteristics of one integrated circuit device. Similarly, in some embodiments such analysis may be performed over all anticipated operating temperatures, and in other embodiments the analysis may be specific to the present operating temperature. In FIG. 14, the digital circuit block 1402 is connected to switching voltage regulator producing supply voltage VDDD, analog circuit block 1404 is connected to switching voltage regulator producing supply voltage VDDH, and analog circuit block 1406 is connected to switching voltage regulator producing supply voltage VDDA. In the following examples, it is assumed that the analog and digital circuit blocks on the chip have control of the three off-chip switching voltage regulators.

[0050] FIG. 15 is a block diagram of the digital circuit block 1402 of the hierarchical dynamic voltage scaling system, in accordance with some embodiments. As shown in FIG. 15, the digital circuit block 1402 includes multiple circuit blocks‘C’, which may correspond to various digital circuits used in a transceiver system. For instance, digital circuit‘D’ may take the form of a ring oscillator, among various other types of digital circuits. As shown, each digital circuit is configured to receive voltage VDDD from the switching voltage regulator. FIG. 15 further includes a digital monitoring circuit configured to receive VDDD. In some embodiments, the digital monitoring circuit is composed of a digital circuit corresponding to a copy of one of the digital circuits‘D’. In some embodiments, the digital monitoring circuit is a copy of the most sensitive circuit of the plurality of digital circuits‘D’. In at least one embodiment, the digital monitoring circuit is a ring oscillator circuit composed of e.g., CMOS inverters. In such an embodiment, the ring oscillator circuit receives voltage VDDD from the switching voltage regulator and operates at a corresponding frequency. The digital monitoring circuit may use a frequency detector to analyze the output of the ring oscillator circuit and may responsively provide a control signal to the switching voltage regulator to either increase or decrease VDDD. In some embodiments, process variation and/or temperature variation may cause slight differences in ring oscillator operation between different chips, and such a dynamic digital voltage scaling circuit 1402 may monitor itself to reduce power consumption. Furthermore, aging may cause circuit elements to slow down, and thus ensuring the digital monitoring circuit is operational in the margin depicted by the vdda max and vdda min curves accounts for such variations over time.

[0051] FIG. 18 is a graph of voltage-scaled trend lines of a plurality of variations of a ring oscillator over various comers in accordance with some embodiments. In FIG. 18, the ring oscillator is simulated to generate voltage-scaled trend lines for standard V threshold (SVT) transistors, low Vt (LVT) transistors, and ultra-low Vt (ULVT) transistors. Furthermore, for each type of transistor, the ring oscillator is further simulated according to small-width transistors (XI) and large-width transistors (X4). The six monitoring circuit curves correspond to voltage-scaled trend lines that define supply voltages VDDD at each comer that significantly reduce power consumption while maintaining sufficient circuit performance and sensitivity. The‘vdda max’ and‘vdda min’ curves illustrate the margin for which the digital monitoring circuit reliably operates. By maintaining the dynamically scaled voltage VDDD above the ‘vdda min’ curve at each comer, the monitoring circuit (and thus each digital circuit‘D’) will operate at a reliable performance. Furthermore, by maintaining the dynamically-scaled voltage VDDD below the‘vdda max’ curve, the digital monitoring circuit consumes power that is less than a predetermined threshold. In some embodiments, generating the‘vdda max’ curve and ‘vdda min’ curve may be done by manually adjusting the supply voltage provided to the digital monitoring circuit and observing the output and power consumption of the digital monitoring circuit. In circuit runtime, however, the circuit may be configured to analyze VDDD and to periodically adjust VDDD via a control signal provided to the switching voltage regulator as described above.

[0052] FIG. 16 is a block diagram of an analog circuit block 1404, in accordance with some embodiments. The analog circuit block 1404 may include a block of analog mission-mode circuits ‘A1-A4’, that may be composed of circuits such as drivers, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). In some embodiments, the mission-mode circuits‘A1-A4’ may be grouped according to supply voltage requirements over a plurality of test comers. Voltage-scaled trendlines such as those shown in FIGs. 18-20 may assist in performing such groupings. The set of mission-mode circuits may include circuits that are not as sensitive to process variation as compared to the digital circuits described above and more sensitive analog circuits such as sheers described below. As shown, analog circuit block 1404 includes a set of analog mission-mode circuits‘ Al’ and‘ A2’ connected directly to VDDH, and a set of analog circuits‘A3’ and‘ A4’ connected to a local on-chip linear regulator. The number of analog mission-mode circuits‘A1-A4’ shown is purely illustrative and should not be considered limiting in any way. Such a hierarchical analog circuit block 1404 may be beneficial if not all analog circuits‘A1-A4’ in the analog circuit block 1404 require the large VDDH voltage provided by the switching voltage regulator. In some embodiments, the analog circuits ‘A and A2’ connected to VDDH may be output drivers that utilize large voltages to drive signals onto a bus, while the analog circuits‘A3’ and‘A4’ connected to the linear regulators may be voltage-controlled oscillators (VCOs) or phase-locked loop (PLL) circuits that utilize smaller voltages. In some embodiments, the linear regulators may also provide low-noise supply voltages to more sensitive circuits. Analog circuit block 1404 further includes two compare-control circuits 1602 and 1604 connected to a reference voltage generator REF configured to generate one or more reference voltages. As shown, compare/ control circuit 1602 is connected directly to VDDH, while compare-control circuit 1604 is connected to the linear regulator. In some embodiments, the compare-control circuit 1602 is configured to receive VDDH and a reference voltage Vrefl from the bandgap reference generator Ref, and to responsively provide a control signal to the switching regulator to align VDDH to the voltage provided by the bandgap reference generator Ref. Similarly, compare-control circuit 1604 is configured to receive a voltage from the linear regulator and a separate reference voltage Vref2, to responsively compare the voltage received from the linear regulator to Vref2, and to responsively provide a control signal to the linear regulator to align the linear regulator voltage to Vref2.

[0053] Such compare-control monitoring circuits in FIG. 16 may be useful in accounting for “IR” drop that may occur to process variation, temperature variation, and aging. In FIG. 16, any resistance in the traces connecting the analog mission-mode circuits‘A1-A4’ to their respective voltage regulators may cause a voltage drop between the regulator and the analog circuit due to the current running through the trace (V = IR). Thus, the compare-control circuits may analyze the output of their respective voltage regulators (after experiencing a similar IR drop), and may control to regulators to increase or decrease voltage so that the desired voltage is seen at the monitoring circuit and is thus seen at the operational analog circuits‘A1-A4’.

[0054] FIG. 17 is a block diagram of an analog circuit block 1406 utilizing dynamic voltage scaling, in accordance with some embodiments. Similar to the analog circuit block 1404 FIG. 16, analog circuit block 1406 includes at least one on-chip linear regulator for scaling VDDA received from the off-chip switching voltage regulator. As shown in FIG. 17, the analog circuit block 1406 includes analog mission-mode circuits ‘A5-A8’, that may include e.g., slicers, demultiplexers (DEMUXs), multiplexers (MUXs), and variable-gain amplifiers (VGAs). Further, the analog circuit block 1406 includes monitoring circuits‘Ml’ and‘M2’ connected to respective compare-control circuits to adjust respective voltage regulators. In some embodiments, the analog mission-mode circuits‘A5’ and A6’ connected to VDDA may include analog circuits such as slicers, DEMUXs, MUXs, and VGAs, while the analog mission mode circuits‘A7’ and‘A8’ connected to the on-chip linear regulator include VCOs and other analog blocks that utilize lower supply voltages than VDDA.

[0055] In some embodiments, the monitoring circuit‘Ml’ may correspond to a sheer circuit path due to the sheer having the most critical path in that particular analog circuit block. Thus, ensuring that the sheer operates correctly will ensure that all other analog circuits‘A5’ and ‘A6’ connected to VDDA in that analog circuit block are also operating correctly. It should be noted that in some embodiments, a monitoring circuit may be configured to measure a plurality of critical circuit paths in addition to the sheer. In such embodiments, a combination of the outputs may be used to control the switching regulator (or the local linear regulator). Such dynamic adjustment may occur responsive to e.g., temperature variation. A particular first critical circuit path may be more sensitive to lower temperatures, and measurements of such a critical circuit path may be selected to provide a control signal while operating temperatures are low. Furthermore, a second critical circuit path may be more sensitive at higher temperatures and measurements of the second critical circuit path may thus be chosen to generate the control signal for updating the corresponding voltage regulator. In some embodiments, the selection between the first and second critical circuit paths within the monitor circuit may be dynamically performed by selecting the worst-case critical path by comparing the required supply voltages for each critical path of the plurality of critical paths and selecting the highest required supply voltage, guaranteeing sufficient operation of the rest of the critical circuit paths.

[0056] In FIG. 17, monitoring circuit‘Ml’ may be a copy of a sheer corresponding to one of analog mission-mode circuits‘ A5’ and‘ A6’ and connected to VDDs. Such a monitoring circuit is shown in FIG. 6 as monitoring circuit 620. As shown in FIG. 6, monitoring circuit 620 includes copy sheer 625. Copy sheer 625 is configured to receive a fixed current (Islicer) produced via VDDS, which may be some external supply, e.g., a 3.3V supply, that is sufficient for a good representation of the desired sheer speed and sensitivity. An estimate of VDDA VDDAestim is produced internally via Islicer, which is compared to the real value of VDDA produced by the switching voltage regulator, and a control signal produced by DIG CTL comparing VDDA to VDDAestim is provided to the switching voltage regulator to adjust VDDA until VDDA matches VDDAestim. Such an embodiment may be easier to control compared to the type of monitoring circuit shown in FIG. 11.

[0057] In some embodiments,‘Ml’ and the compare-control circuit may correspond to the embodiment previously described with respect to FIG. 11. In such embodiments,‘Ml’ may be a copy of a sheer circuit used as e.g., analog circuit‘A5’, receiving VDDA, represented in this particular embodiment by the dotted line.‘Ml’ may be configured to obtain a programmable sensitivity voltage (e.g., 0.25V) setting the desired sensitivity level from e.g., VDDS.‘Ml’ also obtains the supply voltage VDDA from the switching voltage regulator producing VDDA. In such an embodiment, the copy sheer‘Ml’ operates on a periodic test signal and is powered by the VDDA and the programmable sensitivity voltage to generate a control signal using a digital counter 1115 and a DAC 1120, the control signal provided to switching voltage regulator 1125 to update VDDA until the DC output of the comparison circuit matches the programmable sensitivity voltage.

[0058] In at least one alternative embodiment, the monitoring circuit may forego the copy sheer 1105, and may instead monitor the output of a“mission mode” sheer (e.g., analog circuit ‘ A5’ could be the mission mode sheer). In such embodiments, the monitoring circuit‘Ml’ may include the delay element shown in FIG. 11, as well as XOR gate 1110, and may analyze the low-pass filtered output using the programmable sensitivity voltage set to achieve desired sensitivity.

[0059] FIG. 19 is a waveform diagram illustrating voltage-scaled trend lines of sheer (utilizing PMOS gates) and Mux/Demux monitoring circuits, in addition to the designed variation margin curves (the vdda_max_slicer and vdda_min_slicer curves). As previously described, the circuit operating in the most sensitive critical circuit path may be chosen as the monitoring circuit, which from FIG. 19 can be determined to be the sheer circuit. For any given comer along the voltage-scaled trend line, the sheer utilizes a higher supply voltage VDDA than Mux/Demux circuits, as indicated by the Mux/Demux voltage-scaled trendline, and thus the Mux/Demux voltage-scaled trendline conforms to the voltage-scaled trendline of the sheer. In some embodiments,“conforming” may mean that the voltage-scaled trend line of the most critical path indicates use of a higher supply voltage than any other circuit path in the associated circuit block. The Mux/Demux voltage-scaled trend line uses a lower supply voltage VDDA at any given comer than the sheer and is thus less sensitive. The monitoring circuit M2 may operate in a similar fashion and may include a copy of one or more of analog circuits‘A7’ or‘A8’, e.g., a VCO, and may provide a control signal to adjust the supply voltage of local linear regulator. If an intersection of the sheer and Mux/Demux monitoring circuits were to occur, then at any given operating condition either the measured performance of the sheer or Mux/Demux monitoring circuit could be used to adjust the supply voltage, depending on which measured performance required a higher supply voltage.

[0060] FIG. 20 is a waveform diagram of a voltage-scaled trend line of a sheer using NMOS and PMOS circuits across various process comers e.g., fast-fast (FF), fast-slow (FS), slow-fast (SF), slow-slow (SS), and amongst high and low interconnection resistance (R) and capacitance (C) comers RCHH and RCLL, respectively. As shown, the voltage-scaled trend line conforms between the max and min sheer margin, only approaching the margins at the FF RCHH, SS RCHH, and SF RCLL comers. As the PMOS-only sheer has a better-performing voltage- scaled trend line as illustrated in FIG. 19, the PMOS-only sheer may be preferred.

[0061] When grouping circuits together as described in the above embodiments, several factors may be taken into account, including the magnitude of the supply voltage a given circuit uses, the voltage-scaled trend line of the circuit across various process comers and temperature comers (and potentially grouping circuits according to the most common/important comers), as well as what type of circuit it is (digital vs. analog). Examples of such grouping are illustrated in FIG. 22 and FIG. 23. Several other factors may be considered as well. As previously described, other embodiments may perform such analysis specific to the particular process characteristics of a specific integrated circuit instance. Further embodiments may additionally constrain supply voltage scaling considerations to a particular temperature. Voltage scaling adjustments may be performed continuously during normal operation, periodically during normal operation, periodically during interruptions of normal operation, or as part of a one time initialization or start-up procedure.

[0062] Adjustment of supply voltage may be based on predetermined calculations incorporating expected process control variations across a statistically significant number of integrated circuit instances, or may be specific to the particular operational characteristics of a singular device. Such calculations may be done numerically, digitally, or in the analog domain. In some embodiments, said calculations may in whole or in part utilize precomputed elements read from one or more lookup tables.

[0063] In some embodiments, a monitoring circuit may be configured to measure circuit performance of a critical path and to responsively adjust the dynamically-adjusted supply voltage until the dynamically-adjusted supply voltage provides sufficient circuit operation. The monitoring circuit may be configured to apply a variation margin to the dynamically-adjusted supply voltage to ensure sufficient circuit operation across e.g., variation in temperature. The monitoring circuit may subsequently be turned off to save power. In some embodiments, the monitoring circuit may be re-enabled periodically to re-measure circuit performance in the critical path and may make further adjustments to the dynamically- adjusted supply voltage.

[0064] The variation margin may correspond to a fixed voltage to add onto the dynamically- adjusted supply voltage, e.g. 0.05-0. IV. Alternatively, the variation margin may be a percentage, e.g., an extra 10% of margin added to the dynamically-adjusted supply voltage once the measured circuit performance of the critical path has been deemed sufficient.

[0065] FIG. 13 is a flowchart of a method 1300, in accordance with some embodiments. As shown, method 1300 includes obtaining 1302 a periodic test signal, and sampling 1304 the periodic test signal using a sampling element 1105 according to a sampling clock ck to generate a sampled periodic output Q, the sampling element 1105 operating according to a supply voltage VDDA provided by a voltage regulator 1125, the voltage regulator 1125 providing the supply voltage VDDA according to a supply voltage control signal. The sampled periodic output Q is compared 1306 to the sampling clock ck to generate a clock-to- Q measurement indicative of a delay value associated with the generation of the sampled periodic output Q in response to the sampling clock ck. The supply voltage control signal is generated 1308 based at least in part on an average of the clock-to-Q measurement, and the supply voltage is provided 1310 to a data sampling element (not shown) connected to the voltage regulator 1125, the data sampling element being a replica of the sampling element 1105, the data sampling element sampling a stream of input data according to the sampling clock.

[0066] In some embodiments, the periodic test signal is generated from the sampling clock.

In such embodiments, the periodic test signal may be an attenuated version of the sampling clock. In some embodiments, the sampling clock has a delay with respect to the periodic test signal.

[0067] In some embodiments, generating the supply voltage control signal includes comparing the average of the clock-to-Q measurement to a predetermined operating threshold. In such an embodiment, the comparison may be performed by comparing a duty cycle of the clock-to-Q measurement to the predetermined operating threshold. In some embodiments, the predetermined operating threshold corresponds to a duty cycle of 25%.

[0068] Alternatively, comparing the average of the clock-to-Q measurement to the predetermined operating threshold may include comparing an average value of the clock-to-Q measurement to the predetermined operating threshold. In such embodiments, the predetermined operating threshold corresponds to an average value of 0.25.

[0069] In some embodiments, comparing the sampled periodic output to the sampling clock comprises performing a phase comparison between the sampled periodic output and the sampling clock. In such embodiments, the phase comparison is performed using an exclusive OR (XOR) phase comparator 1110. In some embodiments, the phase comparison is provided to a loop filter.

[0070] In some embodiments, a digital block is used to control the supply voltage by measuring if the delay is too high or too low. If for a number of measurements the votes indicate that delay is high, then the digital unit will command a DAC to increase output voltage by one bit. The increase of DAC would mean an increase in the DC/DC converter. FIG. 12 illustrates such an embodiment used for filtering the votes and updating a DAC to adjust the power supply.

[0071] FIG. 24 is a flowchart of a method 2400, in accordance with some embodiments. As shown, method 2400 includes measuring 2402 performance of a monitoring circuit based on a dynamically- adjusted supply voltage of a respective switching voltage regulator, the monitoring circuit representative of a respective set of mission mode circuits operating in a transceiver signal processing path, the respective set of mission mode circuits grouped according to voltage supply requirements over a plurality of test comers. The method further includes generating 2404 a control signal based on the measured performance of the monitoring circuit and adjusting 2406 the dynamically-adjusted supply voltage of the respective switching voltage regulator based on the generated control signal.

[0072] In some embodiments, the measured performance of the monitoring circuit corresponds to a measurement of a critical circuit path in the set of mission-mode circuits. In some such embodiments, the critical circuit path corresponds to a worst-case-scenario critical circuit path of a plurality of critical circuit paths. The control signal may be dynamically generated based on the worst-case-scenario critical circuit path associated with a given operating condition. In some embodiments, the method further includes identifying the worst- case-scenario critical circuit path by comparing measured performances of the plurality of critical circuit paths.

[0073] In some embodiments, the method further includes providing the control signal to a control circuit that adjusts the dynamically-adjusted supply voltage of the respective switching voltage regulator. In some embodiments, the dynamically-adjusted supply voltage of the respective switching voltage regulator is further adjusted based on a variation margin. The variation margin may be a constant voltage component added to the dynamically- adjusted supply voltage of the respective switching voltage regulator. Alternatively, the variation margin may correspond to a percentage margin applied to the dynamically- adjusted supply voltage of the respective switching voltage regulator. In some embodiments, the performance of the monitoring circuit is periodically measured in response to changes in operating conditions.