ADVANCED PROCESSOR

WIPO Patent Application WO2005013061

A3

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

HASS DAVID T (US)
ZAIDI NAZAR A (US)
RASHID ABBAS (US)
MUKHERJEE BASAB (US)
KAZA ROHINI KRISHNA (US)
RAMIREZ RICARDO (US)

PCT/US2004/023871

December 08, 2005

July 23, 2004

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RAZA MICROELECTRONICS INC (US)
HASS DAVID T (US)
ZAIDI NAZAR A (US)
RASHID ABBAS (US)
MUKHERJEE BASAB (US)
KAZA ROHINI KRISHNA (US)
RAMIREZ RICARDO (US)

H04L12/56; G06F12/08; (IPC1-7): G06F15/16; G06F9/30; G06F12/00

US20030088610A1	2003-05-08
US20020046324A1	2002-04-18
US6574725B1	2003-06-03
US20020078121A1	2002-06-20
US20020147889A1	2002-10-10
US20020069328A1	2002-06-06
US20030067930A1	2003-04-10
US20030050954A1	2003-03-13
US20030128712A1	2003-07-10
US6341337B1	2002-01-22
US20030046521A1	2003-03-06
US5867663A	1999-02-02
US6084856A	2000-07-04
US20030041173A1	2003-02-27
US6629268B1	2003-09-30
US20030033507A1	2003-02-13
US6772268B1	2004-08-03
US6665791B1	2003-12-16
US6687903B1	2004-02-03
US20030101440A1	2003-05-29

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