Field

Embodiments of the present disclosure generally relate semiconductor devices, and more particularly to amidine ligand synthesis methods and amidine ligands for semiconductor devices.

Background

The ability to deposit materials with novel properties as thin films on semiconductor device structures may enable new integration and patterning schemes, as well as decrease the number of manufacturing steps. Generally, thin films may be deposited by thermal atomic layer deposition (ALD) or chemical vapor deposition

(CVD), and these films may be of a nanometer size in thickness. These techniques may provide good coverage of complex structures, while minimizing damage to device structures. A consideration in depositing films successfully includes the chemical precursor used in the process, where the chemical precursor generally is a ligand compound complexed with a metal that is to form the film. Generally, the stability and volatility of the ligand-metal complex may impact successful deposition of a film and the final properties of a metal film.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. FIG. 1 schematically illustrates a top view of an example die in wafer form and in singulated form, in accordance with some embodiments.

FIG. 2 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments.

FIG. 3 illustrates a method for synthesis of amidine ligands, in accordance with some embodiments.

FIG. 4 illustrates a method for depositing a thin metal film on a semiconductor substrate surface using amidine ligand metal complexes, in accordance with some embodiments.

FIG. 5 illustrates a system with a semiconductor device with a thin metal film that was deposited using deposition processes and a low molecular weight amidine ligand metal complex precursor, in accordance with some embodiments.

Detailed Description

Embodiments of the present disclosure describe synthesis methods for synthesis of amidines; amidine-metal complexes, which may be used as precursors for deposition methods; thin metal films formed using amidine-metal complexes on semiconductor devices; and semiconductor devices and systems with thin metal films formed using amidine-metal complexes.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The description may use perspective-based descriptions such as top/bottom, side, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.

The description may use the phrases "in an embodiment," or "in

embodiments," which may each refer to one or more of the same or different

embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The term "coupled" may refer to a direct connection, an indirect connection, or an indirect communication.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact. By way of example and not limitation, "coupled" may mean two or more elements or devices are coupled by electrical connections on a printed circuit board such as a motherboard, for example. By way of example and not limitation, "coupled" may mean two or more elements/devices cooperate and/or interact through one or more network linkages such as wired and/or wireless networks. By way of example and not limitation, a computing apparatus may include two or more computing devices "coupled" by one or more network linkages.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, state machine, and/or other suitable components that provide the described functionality.

In various embodiments, one or more thin metal films may be formed on semiconductor devices. The thin metal films may be formed using any suitable process or processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or physical vapor deposition (PVD). The films may include one or more selected metals and other atoms and/or compounds in selected proportions to impart desired properties to a semiconductor device. Thin metal films may provide certain functions to semiconductor devices related to electrical performance of such devices. In deposition processes, a precursor is used and may be comprised of a metal complexed with an organic compound. The precursor may be subsequently deposited on a surface to form a metal film, after further processing to remove the organic compound. The metal film may be the result of several processing steps, which may include use of one or more gases and/or co-reactants. The organic compound used to form a complex may be referred to as a ligand. The choice of ligand generally may have a strong impact on the ability to effectively form a metal film via deposition processes with the desired properties and performance. Thin metal films may be fractions of a nanometer

(monolayer) up to several micrometers. Some thin metal films useful in semiconductor devices may be from about 1 nanometer up to about 5 nanometers, where these films may provide selected functionality related to resistivity and barrier properties. Deposition methods optionally may include plasma enhanced deposition.

Regarding ALD, this method generally is a serf-limiting thin film growth process in which a heated substrate may be exposed to one or more precursor compounds to form a thin film comprised of the precursor compound(s). The heated substrate may be exposed to one or more co-reactant compounds in addition to the one or more precursor compounds. For example, the heated substrate may be exposed to the co-reactant compounds in a separate operation from the exposure to the precursor compounds. In some embodiments, the exposure to the precursor compound and/or co- reactant compound may be repeated (e.g., additional precursor and/or co-reactant may be added in a sequential manner). The precursor and/or co-reactant both may be in a gas phase when exposed to the heated substrate. The ALD process may be self-limiting because reaction stops after all reactive sites of the substrate are reacted. The ALD process may be characterized by highly conformal and uniform, self-limited film growth, which may allow for control of ultrathin (less than 300 A) film deposition at relatively low temperatures (80 - 450 °C, depending on precursor characteristics).

Success of an ALD process may depend on the choice and design of a chemical precursor. In some embodiments, the precursor may be composed of a metal or main group element, stabilized by an organic ligand framework

Regarding CVD, this method generally is a chemical process that may be used in the semiconductor industry to produce thin films of various compositions. In typical CVD, a substrate may be exposed to a volatile precursor that may react and/or decompose on the substrate surface to produce a thin film, such as a thin metal film. There may be volatile by-products produced during the CVD process. These byproducts may be removed by gas flow through the CVD reaction chamber.

To form a thin film of a metal or a metal containing material on a semiconductor substrate via deposition processes, selected materials may be used including precursors, co-reactants, and/or gases. The precursors generally are comprised of the metal complexed with an organic compound— a ligand as previously described. To form the organic-metal complex, the ligand needs to have certain bonding abilities that allow it to coordinate with the metal. The number of ligands coordinated with a selected metal depends on the coordination number of the metal. For example, a ligand-metal complex may be comprised of numerous ligands for each metal atom, depending on the coordination number of the metal. The coordination number of a metal may be variable.

Some ligands suitable to complex with metals may include the one illustrated in Structure I below, which is an amidine compound.

In Structure I, R1 is an isopropyl group or a tert-butyl group and R2 is a methyl group. Generally, Structure I may be used with a number of first row transition metals such as iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), copper (Cu), and silver (Ag) to form an amidine ligand metal complex, as illustrated by Structure II below. The amidine ligand metal complex may be referred to as an amidinate.

In Structure II, M is the metal that is complexed by the ligand of Structure I, L represents additional ligands of Structure I complexed to metal M, and n is the number of additional ligands, according to the coordination number of metal M. U may be referred to as a ligand array or ancillary ligand array. The coordination number may be referred to as a ligancy. The coordination number for a specific metal may be variable, as previously described. Structure I generally may be unsuitable for higher coordination number metals useful for thin films on semiconductor devices because of steric hindrance associated with too many of the ligands attempting to coordinate with the metal to satisfy the higher coordination number. In other words, Structure I, and similar structures, may be too large to have the proper number of ligands complexed with the metal to satisfy the coordination number of the metal. Examples of higher coordination number metals include but are not limited to titanium (Ti), ruthenium (Ru), tungsten (W), vanadium (V), and molybdenum (Mo). The use of Structure I, and similar structures, to complex with higher coordination number metals generally has been mostly

unsuccessful for purposes of depositing thin films because of volatility and/or thermal stability problems associated with such complexes.

As described above, amidine ligands may be used as stabilizing scaffolds for metal precursors. However, most widely used and commercially available amidine ligands, such as Structure I, generally may be unsuited for a number of metals due to their sterically bulky structures, which may compromise precursor volatility and stability as described above. Lower molecular weight and/or unsymmetrical amidinates may be better suited for metals with higher coordination numbers; however, these amidine ligands generally have not been used commercially for use as stabilizing scaffolds because of the difficulties associated with synthesis of such ligands. Additionally, some of these ligands have not been synthesized. Unsymmetrical structures may be better because these structures generally form ligand-metal complexes that have higher volatility and thus may be better suited to deposition processes. Unsymmetrical structures include structures in which the group bonded to N1 (N) and the group bonded to N2 (Ν') are different groups, as illustrated below for Structure III in Synthesis Scheme I. In accordance with naming conventions, N1 refers to the single bonded nitrogen of the amidine and N2 refers to the double bonded nitrogen of the amidine. As a non-limiting example of an unsymmetrical structure, the group bonded to N1 may be an ethyl group, and the group bonded to N2 may be a methyl group, as illustrated in Structure III below. To synthesize such ligands generally requires specialized equipment, high pressure conditions, and/or the use of large amounts of transition metal salts as catalysts, all of which may make the costs of such ligands commercially unviable as a stabilizing scaffold for thin film deposition. Consequently, the selection of metals that may be complexed by an amidine ligand for deposition processes may be limited. Additionally, even when a certain metal is complexed with a larger molecular weight amidine ligand, the resulting film deposited may not have the properties required.

In some embodiments, a low cost, commercially scalable synthesis route is provided to synthesize amidines for use as stabilizing scaffolds for metal precursors in deposition processes. The synthesis route may be used to synthesize a low

molecular weight amidine. The amidine may be unsymmetrical. The synthesis route may not require the use of specialized and/or excessively costly equipment to perform the synthesis. The resulting low molecular weight amidine generally may be used to complex with high coordination number metals that may be difficult to complex with larger molecular weight amidines, as described above.

In some embodiments, a low molecular weight amidine may be synthesized by a process illustrated in Synthesis Scheme I below.

Synthesis Scheme I may use N-methy lacetam ide as a starting material, as illustrated. N-methylacetamide also may be referred to as N-methyl ethanamide. Other starting materials that may be used include N-methyl propanamide and N-methyl butanamide, by way of example and not limitation. In the synthesis, N-methylacetamide may be subjected to O-alkylation with methyl triflate to yield the corresponding activated imine, as illustrated. O-alkylation or O-alkylating may be referred to as methylation. Methyl triflate also may be referred to as methyl trifluoromethanesulfonate and has the formula Methyl triflate is a powerful methylating reagent. Other

methylating reagents may be used, such as methyl fluorosulfonate, which has the formula The O-alkylation may be carried out at a temperature of

approximately 0 to 30 °C for approximately 10 minutes to 48 hours in ether,

tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or f luorobenzene, by way of example and not limitation.

An activated imine, as illustrated, may be used in-situ as a convenient intermediate to introduce a variety of N-alkyl amines, effectively allowing the

construction of unsymmetrical amidines with different N1-alkyl groups. In Synthesis Scheme I, ethyl amine is substituted for the methoxy group to provide an N1 -ethyl group, as illustrated. Other N-alkyl amines may include methyl amine, propyl amine, and butyl amine, by way of example and not limitation. The N-alkyl amine reaction may be carried out at a temperature of approximately 0 to 30 °C for approximately 10 minutes to 48 hours in ether, tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or fluorobenzene, by way of example and not limitation.

Deprotonation with common bases may allow the isolation of the free amidine, as illustrated in Synthesis Scheme I, Structure III. Common bases may include sodium hydroxide, potassium hydroxide, and ammonium hydroxide, by way of example and not limitation. The deprotonation may be carried out at a temperature of

approximately 0 to 30 °C for approximately 10 minutes to 48 hours in ether,

tetrahydrofuran, methylene chloride, or toluene, for example. Other solvents may include dichloroethane, bromobenzene, or fluorobenzene, by way of example and not limitation.

In some embodiments, the Synthesis Scheme I may be a high-yielding and scalable synthetic protocol for the preparation of low molecular weight amidines in a single reaction chamber using commercially available and easily accessible reagents. Synthesis Scheme I may be highly amenable to industrial scale up for commercial production of low molecular weight amidines. These low molecular amidines may be suitable for complexing with high coordination number metals for using in deposition processes. Synthesis Scheme I may be performed using one or more batch reactors such as constant stirred tank reactor, for example, or using one or more continuous flow reactors alone or in combination with one or more batch reactors. The amidine compounds of Synthesis Scheme I may be purified by using one or more

purification/separation methods such as evaporation, distillation, chromatography, crystallization, filtration, and/or decantation, by way of example and not limitation.

Structure III of Synthesis Scheme I may be complexed with one or more metals to provide an amidinate as illustrated by Structure IV below.

Structure III may be used advantageously to complex with metals of higher coordination numbers where structures of higher molecular weight, such as Structure I, may not be suitable to complex with the higher coordination number metals. Examples of higher coordination number metals include but are not limited to Ti, Ru, W, V, and Mo, as identified previously. Structure III may be generalized as illustrated below by Structure V.

In Structure V, R1 and R3 may be hydrogen, methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1 -methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3-methylbutyl, or 2-methylbutyl groups. In some embodiments, R1 and R3 are not the same group in order to provide an unsymmetric amidine. In Structure V, R2 may be hydrogen, methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1 -methylpropyl, 2-methylpropyl, 1 ,1- dimethylethyl, 3-methylbutyl, or 2-methylbutyl groups.

Generalized Structure V may form amidinates with metals as illustrated in Structure VI below.

As with Structure V, R1 and R3 of Structure VI may be hydrogen, methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1 -methylpropyl, 2-methylpropyl, 1 ,1- dimethylethyl, 3-methylbutyl, or 2-methylbutyl groups. In some embodiments, R1 and R3 are not the same group in order to provide an unsymmetric amidine. In some embodiments, metal M may include Ti, Ru, W, V, or Mo.

In some embodiments, amidinates of Structure VI may be used in deposition processes to deposit a film of Structure VI on a semiconductor substrate. The semiconductor substrate may be further processed to form the film into a metal film. Further processing may include heating the semiconductor to form the metal film. The metal film formed thereon may include residual amounts of the corresponding amidine or decomposition products of the corresponding amidine.

In an embodiment, a laboratory level method of Synthesis Scheme I ("method") may include dissolving N-methylacetamide (1.34 grams, 18.3 millimoles) in 15 milliliters of dry dichloromethane (CH2CI2) under nitrogen and then cooling the solution in an ice bath. The method further may include dissolving methyl trrflate

(MeOTf) (3.0 grams, 18.3 millimoles) in 15 milliliters of and adding, via a syringe, the resulting solution to the N-methylacetamide solution and stirring at room

temperature overnight (approximately 12 hours). The mixture of the two solutions may be clear. The method further may include removing volatile compounds by a vacuum to yield a viscous oil or solid, depending on the conditions. The method further may include dissolving the viscous oil or solid in 20 mL of dry tetrahydrofuran (THF) and cooling the mixture in an ice bath. The method further may include adding a solution of ethylamine in THF ( 2 molar THF solution, 20 millimoles, 10 milliliters) to the dissolved viscous oil or solid solution. The resulting mixture may be a clear yellow solution. The method further may include stirring overnight (approximately 12 hours) under nitrogen at room temperature the clear yellow solution. The method further may include

concentrating the solution to approximately half of its original volume using a vacuum.

The method further may include adding a methanolic solution of sodium hydroxide (NaOH) (20.1 millimoles, 0.81 grams in methanol). The volume of methanol may not affect the reaction at this stage. The method further may include stirring overnight the resulting mixture under nitrogen at room temperature. The method further may include removing the solvent and volatiles using a vacuum to provide a residue. The method further may include dissolving the residue in CH2CI2. The ChfeCb may induce precipitation of sodium triflate (NaOTf). The method further may include filtering the mixture to obtain a solid cake. The method further may include washing the cake may twice with CH2CI2. The method further may include removing the CH2CI2 using a rotary evavorator to provide a crude material that may be a yellow-brown oil. The method further may include trap-to-trap distillation of the crude material under vacuum (0.1 Torr) with the aid of a dry ice/acetone bath. Under these conditions, distillation of the title product as a clear oil may begin at about 80 °C. The final yield may be approximately 1.55 grams, which may be approximately 83-85% purity of Structure III.

FIG. 1 schematically illustrates a top view of an example die 102 in wafer form 10 and in singulated form 100, in accordance with some embodiments. In some embodiments, the die 102 may be one of a plurality of dies (e.g., dies 102, 103a, 103b) of a wafer 11 composed of semiconductor material such as, for example, silicon or other suitable material. The plurality of dies may be formed on a surface of the wafer 11. Each of the dies may be a repeating unit of a semiconductor product that includes one or more transistor assemblies and/or other device assemblies that include thin metal films formed by a deposition process using the low molecular weight amidines in complexes with metals as precursors as disclosed herein. For example, the die 102 may include circuitry having transistor structures 104 and/or other device structures with thin films deposited using the materials and processes described herein for the low molecular weight amidines used to form metal complexes for precursors in deposition processes. Although the transistor structures 104 are depicted in rows that traverse a substantial portion of the die 102 in FIG. 1 for the sake of simplicity, it is to be understood that the transistor structures 104 may be configured in any of a wide variety of other suitable arrangements on the die 102 in other embodiments, including, for example, vertical and horizontal features having much smaller dimensions than depicted. After a fabrication process of the semiconductor product embodied in the dies is complete, the wafer 11 may undergo a singulation process in which each of the dies (e.g., die 102) is separated from one another to provide discrete "chips" of the semiconductor product. The wafer 11 may be any of a variety of sizes. In some embodiments, the wafer 11 has a diameter ranging from about 25.4 mm to about 450 mm. The wafer 11 may include other sizes and/or other shapes in other embodiments. According to various embodiments, the transistor structures 104 may be disposed on a semiconductor substrate in wafer form 10 or singulated form 100. The transistor structures 104 described herein may be incorporated in a die 102 for logic or memory, or combinations thereof. In some embodiments, the transistor structures 104 may be part of a system-on-chip (SoC) assembly.

FIG. 2 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly 200, in accordance with some embodiments. In some

embodiments, the IC assembly 200 may include one or more dies (hereinafter "die 102") electrically and/or physically coupled with a package substrate 121. In some embodiments, the package substrate 121 may be electrically coupled with a circuit board 122, as can be seen. In some embodiments, an integrated circuit (IC) assembly 200 may include one or more of the die 102, package substrate 121 and/or circuit board 122, according to various embodiments. Embodiments described herein for thin metal films may be incorporated in the one or more die 102, according to various

embodiments. The thin metal films may be formed using deposition processes and the amidine ligand-metal complexes described and disclosed herein.

The die 102 may represent a discrete product made from a semiconductor material (e.g., silicon) using semiconductor fabrication techniques such as thin film deposition, lithography, etching and the like used in connection with forming CMOS devices. In some embodiments, the die 102 may be, include, or be a part of a

processor, memory, SoC or ASIC. In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not shown) may encapsulate at least a portion of the die 102 and/or die-level interconnect structures 106.

The die 102 can be attached to the package substrate 121 according to a wide variety of suitable configurations including, for example, being directly coupled with the package substrate 121 in a flip-chip configuration, as depicted. In the flip-chip configuration, an active side, S1 , of the die 102 including circuitry is attached to a surface of the package substrate 121 using die-level interconnect structures 106 such as bumps, pillars, or other suitable structures that may also electrically couple the die 102 with the package substrate 121. The active side S1 of the die 102 may include active devices such as, for example, transistor devices. An inactive side, S2, may be disposed opposite to the active side S1 , as can be seen.

The die 102 may generally include a semiconductor substrate 102a, one or more device layers (hereinafter "device layer 102b") and one or more interconnect layers (hereinafter "interconnect layer 102c"). The semiconductor substrate 102a may be substantially composed of a bulk semiconductor material such as, for example, silicon, in some embodiments. The device layer 102b may represent a region where active devices such as transistor devices are formed on the semiconductor substrate. The device layer 102b may include, for example, transistor structures such as channel bodies and/or source/drain regions of transistor devices. The interconnect layer 102c may include interconnect structures (e.g., electrode terminals) that are configured to route electrical signals to or from the active devices in the device layer 102b. For example, the interconnect layer 102c may include horizontal lines (e.g., trenches) and/or vertical plugs (e.g., vias) or other suitable features to provide electrical routing and/or contacts.

In some embodiments, the die-level interconnect structures 106 may be electrically coupled with the interconnect layer 102c and configured to route electrical signals between the die 102 and other electrical devices. The electrical signals may include, for example, input/output (I/O) signals and/or power/ground signals that are used in connection with operation of the die 102.

In some embodiments, the package substrate 121 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate 121 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.

The package substrate 121 may include electrical routing features configured to route electrical signals to or from the die 102. The electrical routing features may include, for example, pads or traces (not shown) disposed on one or more surfaces of the package substrate 121 and/or internal routing features (not shown) such as, for example, trenches, vias or other interconnect structures to route electrical signals through the package substrate 121. For example, in some embodiments, the package substrate 121 may include electrical routing features such as pads (not shown) configured to receive the respective die-level interconnect structures 106 of the die 102.

The circuit board 122 may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, the circuit board 122 may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame

Retardant 4 (FR-4), FR-1 , cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Interconnect structures (not shown) such as traces, trenches, or vias may be formed through the electrically insulating layers to route the electrical signals of the die 102 through the circuit board 122. The circuit board 122 may be composed of other suitable materials in other embodiments. In some embodiments, the circuit board 122 is a motherboard.

Package-level interconnects such as, for example, solder balls 112 may be coupled to one or more pads (hereinafter "pads 110") on the package substrate 121 and/or on the circuit board 122 to form corresponding solder joints that are configured to further route the electrical signals between the package substrate 121 and the circuit board 122. The pads 110 may be composed of any suitable electrically conductive material such as metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and combinations thereof. Other suitable techniques to physically and/or electrically couple the package substrate 121 with the circuit board 122 may be used in other embodiments.

The IC assembly 200 may include a wide variety of other suitable configurations in other embodiments including, for example, suitable combinations of flip-chip and/or wire-bonding configurations, interposers, multi-chip package

configurations including system-in-package (SiP) and/or package-on-package (PoP) configurations. Other suitable techniques to route electrical signals between the die 102 and other components of the IC assembly 200 may be used in some embodiments.

FIG. 3 illustrates a method 300 for synthesis of amidine ligands, in accordance with some embodiments.

The method 300 at 302 may include O-alkylating an N-methyl alkanamide using an O-alkylating reagent to provide a corresponding activated imine of the N- methyl alkanamide. The alkanamide may include one of ethanamide, propanamide, butanamide, pentanamide, 3-methylbutanamide, or 2-methylbutanamide. The O- alkylating reagent may be methyl triflate or methyl fluorosulfonate.

The method 300 at 304 may include substituting the methoxy group of the activated imine with an alky I amine to provide a substituted activated imine. The alky I group of the alkyl amine may be one of methyl, ethyl, propyl, 1-methylethyl, 1- methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, or butyl group.

The method 300 at 306 may include deprotonating the substituted activated imine with a base to provide an N1-alkyl-alkanamidine having the structure shown in Structure V. The R1 and R2 groups may include up to ten carbon atoms. In some embodiments, R1 has a different number of carbon atoms than R2. The bases may include, for example, sodium hydroxide, potassium hydroxide, and/or ammonium hydroxide.

FIG. 4 illustrates a method 400 for depositing a thin metal film on a semiconductor substrate surface using amidine ligand metal complexes, in accordance with some embodiments.

The method 400 at 402 may include placing a semiconductor device in a deposition chamber. The chamber may be a vacuum chamber. The chamber may include one or more ports to provide flow of one or more gases, or gas mixtures, and further may include one or more ports to purge or remove gases and/or reactants from the chamber. The chamber may include a plasma generating device to produce a plasma of a precursor and/or a gas. The chamber may further include a heating element to heat the semiconductor device in the chamber.

The method 400 at 404 may include depositing a thin film of an amidine- metal complex on a surface of the semiconductor device. The metal may include one of Ti, Ru, W, V, or Mo. The amidine may have the structure shown in Structure V. In some embodiments, R1 and R2 are not the same group and are one of methyl, ethyl, propyl, butyl, pentyl, 1 -methylethyl, 1-methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3- methylbutyl, or 2-methylbutyl. In some embodiments, the thin film is deposited by at least one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

The method 400 at 406 may include curing the semiconductor device to form a film of the metal of the amidine-metal complex on the surface of the semiconductor device. The curing may include heating the semiconductor. Heating of the device may consolidate the metal into a film of metal on the device. The amidine of the complex may evaporate during heating of the device. Additionally or alternatively, the amidine may decompose during the heating of the device. The metal film may have residual amidine and/or decomposed amidine constituents attached to the metal film. The semiconductor device may be subjected to further processing to couple one or more further layers of materials to the metal film. The further materials may include conductive and/or dielectric materials in one or more layers. After completion of processing the semiconductor device with the metal film, the device may be packaged and/or coupled with a system, such as a computer and/or mobile device, for example.

Embodiments of the present disclosure may be implemented into a system using any suitable hardware and/or software to configure as desired. FIG. 5 illustrates a system with a semiconductor device with a thin metal film that was deposited using deposition processes and a low molecular weight amidine ligand metal complex precursor, in accordance with some embodiments. The computing device 500 may house a board such as motherboard 502 (e.g., in housing 508). The motherboard 502 may include a number of components, including but not limited to a processor 504 and at least one communication chip 506. The processor 504 may be physically and electrically coupled to the motherboard 502. In some implementations, the at least one communication chip 506 may also be physically and electrically coupled to the motherboard 502. In further implementations, the communication chip 506 may be part of the processor 504. Depending on its applications, computing device 500 may include other components that may or may not be physically and electrically coupled to the

motherboard 502. These other components may include, but are not limited to, volatile memory (e.g., dynamic random access memory (DRAM) 514), non-volatile memory (e.g., read only memory (ROM) 518), flash memory, random access memory (RAM) 516, a graphics processor 526, a digital signal processor, a crypto processor, a chipset 512, an antenna 532, a display, a touchscreen display 536, a touchscreen controller 528, a battery 544, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device 520, a compass 522, microelectromechanical systems (MEMS) sensor 542, a Geiger counter, an accelerometer, a gyroscope, a speaker 534, a camera 510, and a mass storage device (such as hard disk drive), compact disk (CD), digital versatile disk (DVD), controllers 530, microphone 538, and/or jacks 540, and so forth. Not all of these components are illustrated in FIG. 5.

The communication chip 506 may enable wireless communications for the transfer of data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some

embodiments they might not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including WiGig, Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long- Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The

communication chip 506 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 506 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 506 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDM A), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 506 may operate in accordance with other wireless protocols in other embodiments.

The computing device 500 may include a plurality of communication chips 506. For instance, a first communication chip 506 may be dedicated to shorter range wireless communications such as WiGig, Wi-Fi and Bluetooth and a second

communication chip 506 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. The processor 504, communication chip 506, chipset 512, memory chips 514, 516, 518, and other devices with chips shown in computing device 500 may contain thin metal films as described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. The computing device 500 may be a mobile computing device in some embodiments. In further implementations, the computing device 500 may be any other electronic device that processes data.

EXAMPLES

According to various embodiments, the present disclosure describes thin metal films, which may be formed on various semiconductor devices, as provided herein.

Example 1 of a process for synthesizing an amidine may comprise O-

alkylating an alkanamide having a structure using an O-alkylating reagent to provide a corresponding activated imine of the alkanamide; substituting a methoxy group of the activated imine with an alkyl amine to provide a substituted activated imine; and deprotonating the substituted activated imine with a base to provide an alkanamidine having a structure wherein R1 , R2, and R3

include individually up to six carbon atoms.

Example 2 may include the subject matter of Example 1 and other examples herein, wherein the O-alkylating reagent is methyl triflate.

Example 3 may include the subject matter of Example 1 and other examples herein, wherein the O-alkylating reagent is selected from the group consisting of methyl fluorosulfonate, methyl sulfate, and trimethyl oxononium reagent, and combinations thereof.

Example 4 may include the subject matter of Example 1 and other examples herein, wherein R1 is methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1- methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3-methylbutyl, or 2-methylbutyl.

Example 5 may include the subject matter of Example 1 and other examples herein, wherein R2 is methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1- methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3-methylbutyl, or 2-methylbutyl.

Example 6 may include the subject matter of Example 1 and other examples herein, wherein R3 is methyl, ethyl, propyl, butyl, pentyl, 1-methylethyl, 1- methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3-methylbutyl, or 2-methylbutyl.

Example 7 may include the subject matter of Example 1 and other examples herein, wherein the O-alkylating reaction is performed at a temperature from approximately 0 to 30 °C and is for a time span from approximately 10 minutes to 48 hours. Example 8 may include the subject matter of Example 1 and other examples herein, wherein substituting the methoxy group of the activated imine is performed at a temperature from 0 to 30 °C and is for a time span from approximately 10 minutes to 48 hours.

Example 9 may include the subject matter of any one of Examples 1 -8 and other examples herein, wherein R1 has a different number of carbon atoms than R3.

Example 10 may include the subject matter of any one of Examples 1-8 and other examples herein, wherein R1 is an ethyl group and R2 and R3 are methyl groups.

Example 11 of a process for forming a thin metal film on a semiconductor device may comprise placing a semiconductor device in a deposition chamber;

depositing a thin film of an amidine-metal complex on a surface of the semiconductor device; and curing the semiconductor device to form a film of the metal of the amidine- metal complex on the surface of the semiconductor device, wherein the metal includes

one of Ti, Ru, W, V, or Mo, wherein the amidine has a structure wherein

R1 and R3 are not the same group, and R1 , R2, and R3 are one of methyl, ethyl, propyl, butyl, pentyl, 1 -methylethyl, 1 -methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3- methylbutyl, or 2-methylbutyl.

Example 12 may include the subject matter of Example 11 and other examples herein, wherein R1 is ethyl and R2 and R3 are methyl.

Example 13 may include the subject matter of Example 11 and other examples herein, wherein depositing the thin film is by at least one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

Example 14 may include the subject matter of Example 11 and other examples herein, wherein the semiconductor device is heated at a temperature of approximately 80 °C to 450 °C during deposition of the thin film.

Example 15 of a semiconductor device may comprise a semiconductor substrate with a surface; and a thin metal film coupled to the surface, wherein the thin metal film includes one of Ti, Ru, W, V, or Mo and includes trace amounts of an amidine or decomposition products of the amidine, wherein the amidine has a structure

wherein R1 and R3 are not the same group and R1 , R2, and R3 are one

of methyl, ethyl, propyl, butyl, pentyl, 1 -methylethyl, 1 -methylpropyl, 2-methylpropyl, 1 ,1- dimethylethyl, 3-methylbutyl, or 2-methylbutyl.

Example 16 may include the subject matter of Example 14 and other examples herein, wherein R1 is ethyl and R2 and R3 are methyl.

Example 17 of a computing device may comprise a circuit board; and a semiconductor device coupled to the circuit board and including a thin metal film coupled to a surface of the semiconductor device, wherein the thin metal film includes one of Ti, Ru, W, V, or Mo and includes trace amounts of an amidine or decomposition products of the amidine, wherein the amidine has a structure wherein

R1 and R3 are not the same group and R1 , R2, and R3 are one of methyl, ethyl, propyl, butyl, pentyl, 1 -methylethyl, 1-methylpropyl, 2-methylpropyl, 1 ,1-dimethylethyl, 3- methylbutyl, or 2-methylbutyl.

Example 18 may include the subject matter of Example 17 and other examples herein, wherein R1 is ethyl and R2 and R3 are methyl.

Example 19 may include the subject matter of Example 17 and other examples herein, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be

"and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described

embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above- described embodiments. The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize. These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim

interpretation.